modified word # ; refreshed source folders

[fast-forth/master.git] / MSP_EXP430FR4133.asm

diff --git a/MSP_EXP430FR4133.asm b/MSP_EXP430FR4133.asm
index a953b22..26d6f55 100644 (file)
--- a/MSP_EXP430FR4133.asm
+++ b/MSP_EXP430FR4133.asm
@@ -391,6 +391,8 @@ RTS         .set    8       ; P2.3 bit position
                                         ; fCOCLKDIV = 32768 x 488+1) = 16.023 MHz ; measured : 15.99MHz
             MOV     #01E9h,&CSCTL2      ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1E9h
                                         ; fCOCLKDIV = 32768 x 489+1) = 16.056 MHz ; measured : 16.02MHz
+;            MOV     #01EAh,&CSCTL2      ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1E9h
+                                        ; fCOCLKDIV = 32768 x 490+1) = 16.089 MHz ; measured : 16.02MHz
 ; =====================================
             MOV     #64,X
 
@@ -399,7 +401,9 @@ RTS         .set    8       ; P2.3 bit position
     .ENDIF
 
     .IFDEF LF_XTAL
-;            MOV     #0000h,&CSCTL3      ; FLL select XT1, FLLREFDIV=0 (default value)
+; LFXIN : P4.1, LFXOUT : P4.2
+            MOV  #0600h,&PBSEL0         ; SEL0 for only P4.1,P4.2
+;           MOV     #0000h,&CSCTL3      ; FLL select XT1, FLLREFDIV=0 (default value)
             MOV     #0000h,&CSCTL4      ; ACLOCK select XT1, MCLK & SMCLK select DCOCLKDIV
     .ELSE
             MOV     #0010h,&CSCTL3      ; FLL select REFCLOCK, FLLREFDIV=0
@@ -409,26 +413,15 @@ RTS         .set    8       ; P2.3 bit position
 
             BIS &SYSRSTIV,&SAVE_SYSRSTIV; store volatile SYSRSTIV with preserving a pending request for DEEP_RST
             CMP #2,&SAVE_SYSRSTIV   ; POWER ON ?
-            JZ      ClockWaitX      ; yes : wait 600ms to stabilize power source
-            .word   0359h           ; no  : RRUM #1,X --> wait still 300 ms...
+            JZ      ClockWaitX      ; yes : wait 800ms to stabilize power source
+            .word   0359h           ; no  : RRUM #1,X --> wait still 400 ms...
                                     ;       ...because FLL lock time = 280 ms
 
-ClockWaitX  MOV     #50000,Y        ;
+ClockWaitX  MOV     #-1,Y           ;
 ClockWaitY  SUB     #1,Y            ; 3 cycles loop
-            JNZ     ClockWaitY      ; 50000x3 = 150000 cycles delay = 150ms @ 1MHz
+            JNZ     ClockWaitY      ; 65535 = 196605 cycles delay = 200ms @ 1MHz
             SUB     #1,X            ;
             JNZ     ClockWaitX      ;
 
-
-; ----------------------------------------------------------------------
-; POWER ON RESET AND INITIALIZATION : RTC REGISTERS
-; ----------------------------------------------------------------------
-
-    .IFDEF LF_XTAL
-; LFXIN : P4.1, LFXOUT : P4.2
-    MOV  #0600h,&PBSEL0   ; SEL0 for only P4.1,P4.2
-    .ENDIF
-
-
-
-
+;WAITFLL     BIT #300h,&CSCTL7         ; wait FLL lock
+;            JNZ WAITFLL