amdgpu: stop reading CC_RB_BACKEND_DISABLE on Vega10

[android-x86/external-libdrm.git] / amdgpu / amdgpu_gpu_info.c

diff --git a/amdgpu/amdgpu_gpu_info.c b/amdgpu/amdgpu_gpu_info.c
index 0970769..c5f5f6f 100644 (file)
--- a/amdgpu/amdgpu_gpu_info.c
+++ b/amdgpu/amdgpu_gpu_info.c
@@ -119,7 +119,7 @@ int amdgpu_query_firmware_version(amdgpu_device_handle dev, unsigned fw_type,
                                  uint32_t *version, uint32_t *feature)
 {
        struct drm_amdgpu_info request;
-       struct drm_amdgpu_info_firmware firmware;
+       struct drm_amdgpu_info_firmware firmware = {};
        int r;
 
        memset(&request, 0, sizeof(request));
@@ -140,7 +140,7 @@ int amdgpu_query_firmware_version(amdgpu_device_handle dev, unsigned fw_type,
        return 0;
 }
 
-int amdgpu_query_gpu_info_init(amdgpu_device_handle dev)
+drm_private int amdgpu_query_gpu_info_init(amdgpu_device_handle dev)
 {
        int r, i;
 
@@ -169,50 +169,58 @@ int amdgpu_query_gpu_info_init(amdgpu_device_handle dev)
        dev->info.vce_harvest_config = dev->dev_info.vce_harvest_config;
        dev->info.pci_rev_id = dev->dev_info.pci_rev;
 
-       for (i = 0; i < (int)dev->info.num_shader_engines; i++) {
-               unsigned instance = (i << AMDGPU_INFO_MMR_SE_INDEX_SHIFT) |
-                                   (AMDGPU_INFO_MMR_SH_INDEX_MASK <<
-                                    AMDGPU_INFO_MMR_SH_INDEX_SHIFT);
+       if (dev->info.family_id < AMDGPU_FAMILY_AI) {
+               for (i = 0; i < (int)dev->info.num_shader_engines; i++) {
+                       unsigned instance = (i << AMDGPU_INFO_MMR_SE_INDEX_SHIFT) |
+                                           (AMDGPU_INFO_MMR_SH_INDEX_MASK <<
+                                            AMDGPU_INFO_MMR_SH_INDEX_SHIFT);
+
+                       r = amdgpu_read_mm_registers(dev, 0x263d, 1, instance, 0,
+                                                    &dev->info.backend_disable[i]);
+                       if (r)
+                               return r;
+                       /* extract bitfield CC_RB_BACKEND_DISABLE.BACKEND_DISABLE */
+                       dev->info.backend_disable[i] =
+                               (dev->info.backend_disable[i] >> 16) & 0xff;
+
+                       r = amdgpu_read_mm_registers(dev, 0xa0d4, 1, instance, 0,
+                                                    &dev->info.pa_sc_raster_cfg[i]);
+                       if (r)
+                               return r;
+
+                       if (dev->info.family_id >= AMDGPU_FAMILY_CI) {
+                               r = amdgpu_read_mm_registers(dev, 0xa0d5, 1, instance, 0,
+                                                    &dev->info.pa_sc_raster_cfg1[i]);
+                               if (r)
+                                       return r;
+                       }
+               }
+       }
 
-               r = amdgpu_read_mm_registers(dev, 0x263d, 1, instance, 0,
-                                            &dev->info.backend_disable[i]);
-               if (r)
-                       return r;
-               /* extract bitfield CC_RB_BACKEND_DISABLE.BACKEND_DISABLE */
-               dev->info.backend_disable[i] =
-                       (dev->info.backend_disable[i] >> 16) & 0xff;
+       r = amdgpu_read_mm_registers(dev, 0x263e, 1, 0xffffffff, 0,
+                                            &dev->info.gb_addr_cfg);
+       if (r)
+               return r;
 
-               r = amdgpu_read_mm_registers(dev, 0xa0d4, 1, instance, 0,
-                                            &dev->info.pa_sc_raster_cfg[i]);
+       if (dev->info.family_id < AMDGPU_FAMILY_AI) {
+               r = amdgpu_read_mm_registers(dev, 0x2644, 32, 0xffffffff, 0,
+                                            dev->info.gb_tile_mode);
                if (r)
                        return r;
 
-               r = amdgpu_read_mm_registers(dev, 0xa0d5, 1, instance, 0,
-                                            &dev->info.pa_sc_raster_cfg1[i]);
+               if (dev->info.family_id >= AMDGPU_FAMILY_CI) {
+                       r = amdgpu_read_mm_registers(dev, 0x2664, 16, 0xffffffff, 0,
+                                                    dev->info.gb_macro_tile_mode);
+                       if (r)
+                               return r;
+               }
+
+               r = amdgpu_read_mm_registers(dev, 0x9d8, 1, 0xffffffff, 0,
+                                            &dev->info.mc_arb_ramcfg);
                if (r)
                        return r;
        }
 
-       r = amdgpu_read_mm_registers(dev, 0x2644, 32, 0xffffffff, 0,
-                                    dev->info.gb_tile_mode);
-       if (r)
-               return r;
-
-       r = amdgpu_read_mm_registers(dev, 0x2664, 16, 0xffffffff, 0,
-                                    dev->info.gb_macro_tile_mode);
-       if (r)
-               return r;
-
-       r = amdgpu_read_mm_registers(dev, 0x263e, 1, 0xffffffff, 0,
-                                    &dev->info.gb_addr_cfg);
-       if (r)
-               return r;
-
-       r = amdgpu_read_mm_registers(dev, 0x9d8, 1, 0xffffffff, 0,
-                                    &dev->info.mc_arb_ramcfg);
-       if (r)
-               return r;
-
        dev->info.cu_active_number = dev->dev_info.cu_active_number;
        dev->info.cu_ao_mask = dev->dev_info.cu_ao_mask;
        memcpy(&dev->info.cu_bitmap[0][0], &dev->dev_info.cu_bitmap[0][0], sizeof(dev->info.cu_bitmap));
@@ -226,6 +234,8 @@ int amdgpu_query_gpu_info_init(amdgpu_device_handle dev)
 int amdgpu_query_gpu_info(amdgpu_device_handle dev,
                        struct amdgpu_gpu_info *info)
 {
+       if ((dev == NULL) || (info == NULL))
+               return -EINVAL;
        /* Get ASIC info*/
        *info = dev->info;