#define ROUND_DOWN(x, y) ((x) & ~__round_mask(x, y))
#define AMDGPU_INVALID_VA_ADDRESS 0xffffffffffffffff
+#define AMDGPU_NULL_SUBMIT_SEQ 0
struct amdgpu_bo_va_hole {
struct list_head list;
struct amdgpu_bo_va_mgr *vamgr;
};
+struct amdgpu_asic_id {
+ uint32_t did;
+ uint32_t rid;
+ char *marketing_name;
+};
+
struct amdgpu_device {
atomic_t refcount;
int fd;
unsigned major_version;
unsigned minor_version;
+ /** Lookup table of asic device id, revision id and marketing name */
+ struct amdgpu_asic_id *asic_ids;
/** List of buffer handles. Protected by bo_table_mutex. */
struct util_hash_table *bo_handles;
/** List of buffer GEM flink names. Protected by bo_table_mutex. */
struct drm_amdgpu_info_device dev_info;
struct amdgpu_gpu_info info;
/** The global VA manager for the whole virtual address space */
- struct amdgpu_bo_va_mgr *vamgr;
+ struct amdgpu_bo_va_mgr vamgr;
/** The VA manager for the 32bit address space */
- struct amdgpu_bo_va_mgr *vamgr_32;
+ struct amdgpu_bo_va_mgr vamgr_32;
};
struct amdgpu_bo {
drm_private void
amdgpu_vamgr_free_va(struct amdgpu_bo_va_mgr *mgr, uint64_t va, uint64_t size);
+drm_private int amdgpu_parse_asic_ids(struct amdgpu_asic_id **asic_ids);
+
drm_private int amdgpu_query_gpu_info_init(amdgpu_device_handle dev);
drm_private uint64_t amdgpu_cs_calculate_timeout(uint64_t timeout);