DRM_FORMAT_RGB565, DRM_FORMAT_XBGR8888,
DRM_FORMAT_XRGB8888 };
-const static uint32_t texture_source_formats[] = { DRM_FORMAT_GR88, DRM_FORMAT_R8, DRM_FORMAT_NV21,
- DRM_FORMAT_NV12, DRM_FORMAT_YVU420_ANDROID };
+const static uint32_t texture_source_formats[] = { DRM_FORMAT_GR88, DRM_FORMAT_R8,
+ DRM_FORMAT_NV21, DRM_FORMAT_NV12,
+ DRM_FORMAT_YVU420_ANDROID, DRM_FORMAT_YVU420 };
static int amdgpu_init(struct driver *drv)
{
drv_add_combinations(drv, texture_source_formats, ARRAY_SIZE(texture_source_formats),
&metadata, BO_USE_TEXTURE_MASK);
+ /*
+ * Chrome uses DMA-buf mmap to write to YV12 buffers, which are then accessed by the
+ * Video Encoder Accelerator (VEA). It could also support NV12 potentially in the future.
+ */
+ drv_modify_combination(drv, DRM_FORMAT_YVU420, &metadata, BO_USE_HW_VIDEO_ENCODER);
+ drv_modify_combination(drv, DRM_FORMAT_NV12, &metadata, BO_USE_HW_VIDEO_ENCODER);
+
/* Android CTS tests require this. */
drv_add_combination(drv, DRM_FORMAT_BGR888, &metadata, BO_USE_SW_MASK);
/* Linear formats supported by display. */
drv_modify_combination(drv, DRM_FORMAT_ARGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
drv_modify_combination(drv, DRM_FORMAT_XRGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
+ drv_modify_combination(drv, DRM_FORMAT_ABGR8888, &metadata, BO_USE_SCANOUT);
drv_modify_combination(drv, DRM_FORMAT_XBGR8888, &metadata, BO_USE_SCANOUT);
/* YUV formats for camera and display. */
/* Potentially tiled formats supported by display. */
drv_modify_combination(drv, DRM_FORMAT_ARGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
drv_modify_combination(drv, DRM_FORMAT_XRGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
+ drv_modify_combination(drv, DRM_FORMAT_ABGR8888, &metadata, BO_USE_SCANOUT);
drv_modify_combination(drv, DRM_FORMAT_XBGR8888, &metadata, BO_USE_SCANOUT);
return 0;
}
uint32_t plane, stride;
struct combination *combo;
union drm_amdgpu_gem_create gem_create;
- struct amdgpu_priv *priv = bo->drv->priv;
combo = drv_get_combination(bo->drv, format, use_flags);
if (!combo)
return -EINVAL;
if (combo->metadata.tiling == TILE_TYPE_DRI) {
+ bool needs_alignment = false;
#ifdef __ANDROID__
/*
* Currently, the gralloc API doesn't differentiate between allocation time and map
*
* See b/115946221,b/117942643
*/
- if (use_flags & (BO_USE_SW_MASK)) {
+ if (use_flags & (BO_USE_SW_MASK))
+ needs_alignment = true;
+#endif
+ // See b/122049612
+ if (use_flags & (BO_USE_SCANOUT))
+ needs_alignment = true;
+
+ if (needs_alignment) {
uint32_t bytes_per_pixel = drv_bytes_per_pixel_from_format(format, 0);
width = ALIGN(width, 256 / bytes_per_pixel);
}
-#endif
+
return dri_bo_create(bo, width, height, format, use_flags);
}
drv_bo_from_format(bo, stride, height, format);
memset(&gem_create, 0, sizeof(gem_create));
- gem_create.in.bo_size = bo->total_size;
+ gem_create.in.bo_size = bo->meta.total_size;
gem_create.in.alignment = 256;
gem_create.in.domain_flags = 0;
if (!(use_flags & (BO_USE_SW_READ_OFTEN | BO_USE_SCANOUT)))
gem_create.in.domain_flags |= AMDGPU_GEM_CREATE_CPU_GTT_USWC;
- /* If drm_version >= 21 everything exposes explicit synchronization primitives
- and chromeos/arc++ will use them. Disable implicit synchronization. */
- if (priv->drm_version >= 21) {
- gem_create.in.domain_flags |= AMDGPU_GEM_CREATE_EXPLICIT_SYNC;
- }
-
/* Allocate the buffer with the preferred heap. */
ret = drmCommandWriteRead(drv_get_fd(bo->drv), DRM_AMDGPU_GEM_CREATE, &gem_create,
sizeof(gem_create));
if (ret < 0)
return ret;
- for (plane = 0; plane < bo->num_planes; plane++)
+ for (plane = 0; plane < bo->meta.num_planes; plane++)
bo->handles[plane].u32 = gem_create.out.handle;
return 0;
return MAP_FAILED;
}
- vma->length = bo->total_size;
+ vma->length = bo->meta.total_size;
- return mmap(0, bo->total_size, drv_get_prot(map_flags), MAP_SHARED, bo->drv->fd,
+ return mmap(0, bo->meta.total_size, drv_get_prot(map_flags), MAP_SHARED, bo->drv->fd,
gem_map.out.addr_ptr);
}
return munmap(vma->addr, vma->length);
}
-static uint32_t amdgpu_resolve_format(uint32_t format, uint64_t use_flags)
+static int amdgpu_bo_invalidate(struct bo *bo, struct mapping *mapping)
+{
+ int ret;
+ union drm_amdgpu_gem_wait_idle wait_idle;
+
+ if (bo->priv)
+ return 0;
+
+ memset(&wait_idle, 0, sizeof(wait_idle));
+ wait_idle.in.handle = bo->handles[0].u32;
+ wait_idle.in.timeout = AMDGPU_TIMEOUT_INFINITE;
+
+ ret = drmCommandWriteRead(bo->drv->fd, DRM_AMDGPU_GEM_WAIT_IDLE, &wait_idle,
+ sizeof(wait_idle));
+
+ if (ret < 0) {
+ drv_log("DRM_AMDGPU_GEM_WAIT_IDLE failed with %d\n", ret);
+ return ret;
+ }
+
+ if (ret == 0 && wait_idle.out.status)
+ drv_log("DRM_AMDGPU_GEM_WAIT_IDLE BO is busy\n");
+
+ return 0;
+}
+
+static uint32_t amdgpu_resolve_format(struct driver *drv, uint32_t format, uint64_t use_flags)
{
switch (format) {
case DRM_FORMAT_FLEX_IMPLEMENTATION_DEFINED:
.bo_import = amdgpu_import_bo,
.bo_map = amdgpu_map_bo,
.bo_unmap = amdgpu_unmap_bo,
+ .bo_invalidate = amdgpu_bo_invalidate,
.resolve_format = amdgpu_resolve_format,
};