/*
- * Copyright (c) 2016 The Chromium OS Authors. All rights reserved.
+ * Copyright 2016 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
+#include <sys/mman.h>
#include <xf86drm.h>
#include <amdgpu_drm.h>
#include <amdgpu.h>
};
static struct supported_combination combos[5] = {
- {DRM_FORMAT_ARGB8888, DRM_FORMAT_MOD_NONE, BO_USE_CURSOR | BO_USE_LINEAR},
- {DRM_FORMAT_ARGB8888, DRM_FORMAT_MOD_NONE, BO_USE_RENDERING},
- {DRM_FORMAT_XBGR8888, DRM_FORMAT_MOD_NONE, BO_USE_RENDERING},
- {DRM_FORMAT_XRGB8888, DRM_FORMAT_MOD_NONE, BO_USE_LINEAR},
- {DRM_FORMAT_XRGB8888, DRM_FORMAT_MOD_NONE, BO_USE_RENDERING},
+ {DRM_FORMAT_ARGB8888, DRM_FORMAT_MOD_NONE,
+ BO_USE_CURSOR | BO_USE_LINEAR | BO_USE_SW_READ_OFTEN | BO_USE_SW_WRITE_OFTEN},
+ {DRM_FORMAT_ARGB8888, DRM_FORMAT_MOD_NONE,
+ BO_USE_RENDERING | BO_USE_SW_READ_RARELY | BO_USE_SW_WRITE_RARELY},
+ {DRM_FORMAT_XBGR8888, DRM_FORMAT_MOD_NONE,
+ BO_USE_RENDERING | BO_USE_SW_READ_RARELY | BO_USE_SW_WRITE_RARELY},
+ {DRM_FORMAT_XRGB8888, DRM_FORMAT_MOD_NONE,
+ BO_USE_LINEAR | BO_USE_SW_READ_OFTEN | BO_USE_SW_WRITE_OFTEN},
+ {DRM_FORMAT_XRGB8888, DRM_FORMAT_MOD_NONE,
+ BO_USE_RENDERING | BO_USE_SW_READ_RARELY | BO_USE_SW_WRITE_RARELY},
};
static int amdgpu_set_metadata(int fd, uint32_t handle,
struct amdgpu_bo_metadata metadata = {0};
ADDR_COMPUTE_SURFACE_INFO_OUTPUT addr_out = {0};
uint32_t tiling_flags = 0;
+ uint32_t gem_create_flags = 0;
int ret;
if (amdgpu_addrlib_compute(addrlib, width,
bo->sizes[0] = addr_out.surfSize;
bo->strides[0] = addr_out.pixelPitch
* DIV_ROUND_UP(addr_out.pixelBits, 8);
+ if (usage & (BO_USE_CURSOR | BO_USE_LINEAR | BO_USE_SW_READ_OFTEN |
+ BO_USE_SW_WRITE_OFTEN | BO_USE_SW_WRITE_RARELY |
+ BO_USE_SW_READ_RARELY))
+ gem_create_flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
+ else
+ gem_create_flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
memset(&gem_create, 0, sizeof(gem_create));
gem_create.in.bo_size = bo->sizes[0];
gem_create.in.alignment = addr_out.baseAlign;
/* Set the placement. */
gem_create.in.domains = AMDGPU_GEM_DOMAIN_VRAM;
- gem_create.in.domain_flags = usage;
+ gem_create.in.domain_flags = gem_create_flags;
/* Allocate the buffer with the preferred heap. */
ret = drmCommandWriteRead(drv_get_fd(bo->drv), DRM_AMDGPU_GEM_CREATE,
return ret;
}
+static void *amdgpu_bo_map(struct bo *bo, struct map_info *data, size_t plane)
+{
+ int ret;
+ union drm_amdgpu_gem_mmap gem_map;
+
+ memset(&gem_map, 0, sizeof(gem_map));
+ gem_map.in.handle = bo->handles[0].u32;
+
+ ret = drmIoctl(bo->drv->fd, DRM_IOCTL_AMDGPU_GEM_MMAP, &gem_map);
+ if (ret) {
+ fprintf(stderr, "drv: DRM_IOCTL_AMDGPU_GEM_MMAP failed\n");
+ return MAP_FAILED;
+ }
+ data->length = bo->sizes[0];
+
+ return mmap(0, bo->sizes[0], PROT_READ | PROT_WRITE, MAP_SHARED,
+ bo->drv->fd, gem_map.out.addr_ptr);
+}
+
struct backend backend_amdgpu = {
.name = "amdgpu",
.init = amdgpu_init,
.close = amdgpu_close,
.bo_create = amdgpu_bo_create,
.bo_destroy = drv_gem_bo_destroy,
+ .bo_import = drv_prime_bo_import,
+ .bo_map = amdgpu_bo_map,
};
#endif