minigbm: add map_info to proper table

[android-x86/external-minigbm.git] / amdgpu.c

diff --git a/amdgpu.c b/amdgpu.c
index a9d6d4c..5dcfbeb 100644 (file)
--- a/amdgpu.c
+++ b/amdgpu.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016 The Chromium OS Authors. All rights reserved.
+ * Copyright 2016 The Chromium OS Authors. All rights reserved.
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,6 +8,7 @@
 #include <stdio.h>
 #include <stdlib.h>
 #include <string.h>
+#include <sys/mman.h>
 #include <xf86drm.h>
 #include <amdgpu_drm.h>
 #include <amdgpu.h>
@@ -38,6 +39,19 @@ enum {
        FAMILY_LAST,
 };
 
+static struct supported_combination combos[5] = {
+       {DRM_FORMAT_ARGB8888, DRM_FORMAT_MOD_NONE,
+               BO_USE_CURSOR | BO_USE_LINEAR | BO_USE_SW_READ_OFTEN | BO_USE_SW_WRITE_OFTEN},
+       {DRM_FORMAT_ARGB8888, DRM_FORMAT_MOD_NONE,
+               BO_USE_RENDERING | BO_USE_SW_READ_RARELY | BO_USE_SW_WRITE_RARELY},
+       {DRM_FORMAT_XBGR8888, DRM_FORMAT_MOD_NONE,
+               BO_USE_RENDERING | BO_USE_SW_READ_RARELY | BO_USE_SW_WRITE_RARELY},
+       {DRM_FORMAT_XRGB8888, DRM_FORMAT_MOD_NONE,
+               BO_USE_LINEAR | BO_USE_SW_READ_OFTEN | BO_USE_SW_WRITE_OFTEN},
+       {DRM_FORMAT_XRGB8888, DRM_FORMAT_MOD_NONE,
+               BO_USE_RENDERING | BO_USE_SW_READ_RARELY | BO_USE_SW_WRITE_RARELY},
+};
+
 static int amdgpu_set_metadata(int fd, uint32_t handle,
                               struct amdgpu_bo_metadata *info)
 {
@@ -148,7 +162,7 @@ static int amdgpu_addrlib_compute(void *addrlib, uint32_t width,
 
        /* Set the requested tiling mode. */
        addr_surf_info_in.tileMode = ADDR_TM_2D_TILED_THIN1;
-       if (usage & (DRV_BO_USE_CURSOR | DRV_BO_USE_LINEAR))
+       if (usage & (BO_USE_CURSOR | BO_USE_LINEAR))
                addr_surf_info_in.tileMode = ADDR_TM_LINEAR_ALIGNED;
        if (width <= 16 || height <= 16)
                addr_surf_info_in.tileMode = ADDR_TM_1D_TILED_THIN1;
@@ -166,7 +180,7 @@ static int amdgpu_addrlib_compute(void *addrlib, uint32_t width,
        addr_surf_info_in.flags.noStencil = 1;
 
        /* Set the micro tile type. */
-       if (usage & DRV_BO_USE_SCANOUT)
+       if (usage & BO_USE_SCANOUT)
                addr_surf_info_in.tileType = ADDR_DISPLAYABLE;
        else
                addr_surf_info_in.tileType = ADDR_NON_DISPLAYABLE;
@@ -283,7 +297,8 @@ static int amdgpu_init(struct driver *drv)
 
        drv->priv = addrlib;
 
-       return 0;
+       drv_insert_combinations(drv, combos, ARRAY_SIZE(combos));
+       return drv_add_kms_flags(drv);
 }
 
 static void amdgpu_close(struct driver *drv)
@@ -300,6 +315,7 @@ static int amdgpu_bo_create(struct bo *bo, uint32_t width, uint32_t height,
        struct amdgpu_bo_metadata metadata = {0};
        ADDR_COMPUTE_SURFACE_INFO_OUTPUT addr_out = {0};
        uint32_t tiling_flags = 0;
+       uint32_t gem_create_flags = 0;
        int ret;
 
        if (amdgpu_addrlib_compute(addrlib, width,
@@ -313,13 +329,19 @@ static int amdgpu_bo_create(struct bo *bo, uint32_t width, uint32_t height,
        bo->sizes[0] = addr_out.surfSize;
        bo->strides[0] = addr_out.pixelPitch
                * DIV_ROUND_UP(addr_out.pixelBits, 8);
+       if (usage & (BO_USE_CURSOR | BO_USE_LINEAR | BO_USE_SW_READ_OFTEN |
+                    BO_USE_SW_WRITE_OFTEN | BO_USE_SW_WRITE_RARELY |
+                    BO_USE_SW_READ_RARELY))
+               gem_create_flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
+       else
+               gem_create_flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
 
        memset(&gem_create, 0, sizeof(gem_create));
        gem_create.in.bo_size = bo->sizes[0];
        gem_create.in.alignment = addr_out.baseAlign;
        /* Set the placement. */
        gem_create.in.domains = AMDGPU_GEM_DOMAIN_VRAM;
-       gem_create.in.domain_flags = usage;
+       gem_create.in.domain_flags = gem_create_flags;
 
        /* Allocate the buffer with the preferred heap. */
        ret = drmCommandWriteRead(drv_get_fd(bo->drv), DRM_AMDGPU_GEM_CREATE,
@@ -338,21 +360,33 @@ static int amdgpu_bo_create(struct bo *bo, uint32_t width, uint32_t height,
        return ret;
 }
 
-const struct backend backend_amdgpu = {
+static void *amdgpu_bo_map(struct bo *bo, struct map_info *data, size_t plane)
+{
+       int ret;
+       union drm_amdgpu_gem_mmap gem_map;
+
+       memset(&gem_map, 0, sizeof(gem_map));
+       gem_map.in.handle = bo->handles[0].u32;
+
+       ret = drmIoctl(bo->drv->fd, DRM_IOCTL_AMDGPU_GEM_MMAP, &gem_map);
+       if (ret) {
+               fprintf(stderr, "drv: DRM_IOCTL_AMDGPU_GEM_MMAP failed\n");
+               return MAP_FAILED;
+       }
+       data->length = bo->sizes[0];
+
+       return mmap(0, bo->sizes[0], PROT_READ | PROT_WRITE, MAP_SHARED,
+                   bo->drv->fd, gem_map.out.addr_ptr);
+}
+
+struct backend backend_amdgpu = {
        .name = "amdgpu",
        .init = amdgpu_init,
        .close = amdgpu_close,
        .bo_create = amdgpu_bo_create,
        .bo_destroy = drv_gem_bo_destroy,
-       .format_list = {
-               /* Linear support */
-               {DRV_FORMAT_XRGB8888, DRV_BO_USE_SCANOUT | DRV_BO_USE_LINEAR},
-               {DRV_FORMAT_ARGB8888, DRV_BO_USE_SCANOUT | DRV_BO_USE_CURSOR | DRV_BO_USE_LINEAR},
-               /* Blocklinear support */
-               {DRV_FORMAT_XRGB8888, DRV_BO_USE_SCANOUT | DRV_BO_USE_RENDERING},
-               {DRV_FORMAT_ARGB8888, DRV_BO_USE_SCANOUT | DRV_BO_USE_RENDERING},
-               {DRV_FORMAT_XBGR8888, DRV_BO_USE_SCANOUT | DRV_BO_USE_RENDERING},
-       }
+       .bo_import = drv_prime_bo_import,
+       .bo_map = amdgpu_bo_map,
 };
 
 #endif