help
The original ARC ISA of ARC600/700 cores
-### For bisectability, disable ARCv2 support until we have all the bits in place
-#config ISA_ARCV2
-# bool "ARC ISA v2"
-# help
-# ISA for the Next Generation ARC-HS cores
+config ISA_ARCV2
+ bool "ARC ISA v2"
+ help
+ ISA for the Next Generation ARC-HS cores
endchoice
Build kernel for Big Endian Mode of ARC CPU
config SMP
- bool "Symmetric Multi-Processing (Incomplete)"
+ bool "Symmetric Multi-Processing"
default n
+ select ARC_HAS_COH_CACHES if ISA_ARCV2
+ select ARC_MCIP if ISA_ARCV2
help
- This enables support for systems with more than one CPU. If you have
- a system with only one CPU, say N. If you have a system with more
- than one CPU, say Y.
+ This enables support for systems with more than one CPU.
if SMP
config ARC_HAS_REENTRANT_IRQ_LV2
def_bool n
-endif #SMP
+config ARC_MCIP
+ bool "ARConnect Multicore IP (MCIP) Support "
+ depends on ISA_ARCV2
+ help
+ This IP block enables SMP in ARC-HS38 cores.
+ It provides for cross-core interrupts, multi-core debug
+ hardware semaphores, shared memory,....
config NR_CPUS
int "Maximum number of CPUs (2-4096)"
range 2 4096
- depends on SMP
- default "2"
+ default "4"
+
+endif #SMP
menuconfig ARC_CACHE
bool "Enable Cache Support"
config ARC_CACHE_VIPT_ALIASING
bool "Support VIPT Aliasing D$"
- depends on ARC_HAS_DCACHE
+ depends on ARC_HAS_DCACHE && ISA_ARCOMPACT
default n
endif #ARC_CACHE
dest operands with 2 possible source operands.
default y
+config ARC_HAS_RTC
+ bool "Local 64-bit r/o cycle counter"
+ default n
+ depends on !SMP
+
+config ARC_HAS_GRTC
+ bool "SMP synchronized 64-bit cycle counter"
+ default y
+ depends on SMP
+
config ARC_NUMBER_OF_INTERRUPTS
int "Number of interrupts"
range 8 240
bool "ARC debugging"
default y
+if ARC_DBG
+
config ARC_DW2_UNWIND
bool "Enable DWARF specific kernel stack unwind"
- depends on ARC_DBG
default y
select KALLSYMS
help
config ARC_DBG_TLB_PARANOIA
bool "Paranoia Checks in Low Level TLB Handlers"
- depends on ARC_DBG
default n
config ARC_DBG_TLB_MISS_COUNT
bool "Profile TLB Misses"
default n
select DEBUG_FS
- depends on ARC_DBG
help
Counts number of I and D TLB Misses and exports them via Debugfs
The counters can be cleared via Debugfs as well
+if SMP
+
+config ARC_IPI_DBG
+ bool "Debug Inter Core interrupts"
+ default n
+
+endif
+
+endif
+
config ARC_UBOOT_SUPPORT
bool "Support uboot arg Handling"
default n