Merge tag 'clock' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

[uclinux-h8/linux.git] / arch / arm / mach-kirkwood / pcie.c

diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c
index de37317..6e8b2ef 100644 (file)
--- a/arch/arm/mach-kirkwood/pcie.c
+++ b/arch/arm/mach-kirkwood/pcie.c
@@ -11,6 +11,7 @@
 #include <linux/kernel.h>
 #include <linux/pci.h>
 #include <linux/slab.h>
+#include <linux/clk.h>
 #include <video/vga.h>
 #include <asm/irq.h>
 #include <asm/mach/pci.h>
@@ -19,6 +20,23 @@
 #include <plat/addr-map.h>
 #include "common.h"
 
+static void kirkwood_enable_pcie_clk(const char *port)
+{
+       struct clk *clk;
+
+       clk = clk_get_sys("pcie", port);
+       if (IS_ERR(clk)) {
+               printk(KERN_ERR "PCIE clock %s missing\n", port);
+               return;
+       }
+       clk_prepare_enable(clk);
+       clk_put(clk);
+}
+
+/* This function is called very early in the boot when probing the
+   hardware to determine what we actually are, and what rate tclk is
+   ticking at. Hence calling kirkwood_enable_pcie_clk() is not
+   possible since the clk tree has not been created yet. */
 void kirkwood_enable_pcie(void)
 {
        u32 curr = readl(CLOCK_GATING_CTRL);
@@ -26,7 +44,7 @@ void kirkwood_enable_pcie(void)
                writel(curr | CGC_PEX0, CLOCK_GATING_CTRL);
 }
 
-void __init kirkwood_pcie_id(u32 *dev, u32 *rev)
+void kirkwood_pcie_id(u32 *dev, u32 *rev)
 {
        kirkwood_enable_pcie();
        *dev = orion_pcie_dev_id((void __iomem *)PCIE_VIRT_BASE);
@@ -159,7 +177,6 @@ static void __init pcie1_ioresources_init(struct pcie_port *pp)
 
 static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
 {
-       extern unsigned int kirkwood_clk_ctrl;
        struct pcie_port *pp;
        int index;
 
@@ -178,11 +195,11 @@ static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
 
        switch (index) {
        case 0:
-               kirkwood_clk_ctrl |= CGC_PEX0;
+               kirkwood_enable_pcie_clk("0");
                pcie0_ioresources_init(pp);
                break;
        case 1:
-               kirkwood_clk_ctrl |= CGC_PEX1;
+               kirkwood_enable_pcie_clk("1");
                pcie1_ioresources_init(pp);
                break;
        default: