sh: implement DMA_SLAVE capability in SH dmaengine driver

[android-x86/kernel.git] / arch / sh / include / cpu-sh4 / cpu / dma-sh4a.h

diff --git a/arch/sh/include/cpu-sh4/cpu/dma-sh4a.h b/arch/sh/include/cpu-sh4/cpu/dma-sh4a.h
index cc1cf3e..e734ea4 100644 (file)
--- a/arch/sh/include/cpu-sh4/cpu/dma-sh4a.h
+++ b/arch/sh/include/cpu-sh4/cpu/dma-sh4a.h
@@ -7,7 +7,7 @@
 #define DMTE4_IRQ      76
 #define DMAE0_IRQ      78      /* DMA Error IRQ*/
 #define SH_DMAC_BASE0  0xFE008020
-#define SH_DMARS_BASE  0xFE009000
+#define SH_DMARS_BASE0 0xFE009000
 #define CHCR_TS_LOW_MASK       0x00000018
 #define CHCR_TS_LOW_SHIFT      3
 #define CHCR_TS_HIGH_MASK      0
@@ -17,7 +17,7 @@
 #define DMTE4_IRQ      76
 #define DMAE0_IRQ      78      /* DMA Error IRQ*/
 #define SH_DMAC_BASE0  0xFE008020
-#define SH_DMARS_BASE  0xFE009000
+#define SH_DMARS_BASE0 0xFE009000
 #define CHCR_TS_LOW_MASK       0x00000018
 #define CHCR_TS_LOW_SHIFT      3
 #define CHCR_TS_HIGH_MASK      0x00300000
@@ -28,7 +28,7 @@
 #define DMTE4_IRQ      44
 #define DMAE0_IRQ      38
 #define SH_DMAC_BASE0  0xFF608020
-#define SH_DMARS_BASE  0xFF609000
+#define SH_DMARS_BASE0 0xFF609000
 #define CHCR_TS_LOW_MASK       0x00000018
 #define CHCR_TS_LOW_SHIFT      3
 #define CHCR_TS_HIGH_MASK      0
@@ -45,7 +45,7 @@
 #define DMAE1_IRQ      74      /* DMA Error IRQ*/
 #define SH_DMAC_BASE0  0xFE008020
 #define SH_DMAC_BASE1  0xFDC08020
-#define SH_DMARS_BASE  0xFDC09000
+#define SH_DMARS_BASE0 0xFDC09000
 #define CHCR_TS_LOW_MASK       0x00000018
 #define CHCR_TS_LOW_SHIFT      3
 #define CHCR_TS_HIGH_MASK      0
@@ -62,7 +62,8 @@
 #define DMAE1_IRQ      74      /* DMA Error IRQ*/
 #define SH_DMAC_BASE0  0xFE008020
 #define SH_DMAC_BASE1  0xFDC08020
-#define SH_DMARS_BASE  0xFDC09000
+#define SH_DMARS_BASE0 0xFE009000
+#define SH_DMARS_BASE1 0xFDC09000
 #define CHCR_TS_LOW_MASK       0x00000018
 #define CHCR_TS_LOW_SHIFT      3
 #define CHCR_TS_HIGH_MASK      0x00600000
@@ -78,7 +79,7 @@
 #define DMAE0_IRQ      38      /* DMA Error IRQ */
 #define SH_DMAC_BASE0  0xFC808020
 #define SH_DMAC_BASE1  0xFC818020
-#define SH_DMARS_BASE  0xFC809000
+#define SH_DMARS_BASE0 0xFC809000
 #define CHCR_TS_LOW_MASK       0x00000018
 #define CHCR_TS_LOW_SHIFT      3
 #define CHCR_TS_HIGH_MASK      0
@@ -95,7 +96,7 @@
 #define DMAE1_IRQ      58      /* DMA Error IRQ1 */
 #define SH_DMAC_BASE0  0xFC808020
 #define SH_DMAC_BASE1  0xFCC08020
-#define SH_DMARS_BASE  0xFC809000
+#define SH_DMARS_BASE0 0xFC809000
 #define CHCR_TS_LOW_MASK       0x00000018
 #define CHCR_TS_LOW_SHIFT      3
 #define CHCR_TS_HIGH_MASK      0