use ieee.std_logic_unsigned.conv_integer;
--
--- MOTO NES FPGA On GHDL Simulation Environment Virtual Cuicuit Board
+-- MOTO NES FPGA On DE0-CV Environment Virtual Cuicuit Board
-- All of the components are assembled and instanciated on this board.
--
entity de0_cv_nes is
- port (
---debug signal
- signal dbg_cpu_clk : out std_logic;
- signal dbg_ppu_clk : out std_logic;
- signal dbg_emu_ppu_clk : out std_logic;
- signal dbg_cpu_mem_clk : out std_logic;
- signal dbg_r_nw : out std_logic;
- signal dbg_addr : out std_logic_vector( 16 - 1 downto 0);
- signal dbg_d_io : out std_logic_vector( 8 - 1 downto 0);
- signal dbg_v_addr : out std_logic_vector (13 downto 0);
- signal dbg_v_data : out std_logic_vector (7 downto 0);
-
----monitor inside cpu
- signal dbg_instruction : out std_logic_vector(7 downto 0);
- signal dbg_exec_cycle : out std_logic_vector (5 downto 0);
- signal dbg_ea_carry : out std_logic;
- signal dbg_status : out std_logic_vector(7 downto 0);
-
---ppu debug pins
- signal dbg_ppu_ce_n : out std_logic;
- signal dbg_ppu_ctrl, dbg_ppu_mask, dbg_ppu_status : out std_logic_vector (7 downto 0);
- signal dbg_ppu_addr : out std_logic_vector (13 downto 0);
- signal dbg_ppu_data, dbg_ppu_scrl_x, dbg_ppu_scrl_y : out std_logic_vector (7 downto 0);
- signal dbg_nmi : out std_logic;
-\r
+ port (\r
--logic analyzer reference clock
signal dbg_base_clk: out std_logic;\r
--NES instance
- base_clk : in std_logic;
- rst_n : in std_logic;
- joypad1 : in std_logic_vector(7 downto 0);
- joypad2 : in std_logic_vector(7 downto 0);
- h_sync_n : out std_logic;
- v_sync_n : out std_logic;
- r : out std_logic_vector(3 downto 0);
- g : out std_logic_vector(3 downto 0);
- b : out std_logic_vector(3 downto 0);
- nt_v_mirror : in std_logic\r
+ pi_base_clk : in std_logic;
+ pi_rst_n : in std_logic;
+ pi_joypad1 : in std_logic_vector(7 downto 0);
+ pi_joypad2 : in std_logic_vector(7 downto 0);
+ po_h_sync_n : out std_logic;
+ po_v_sync_n : out std_logic;
+ po_r : out std_logic_vector(3 downto 0);
+ po_g : out std_logic_vector(3 downto 0);
+ po_b : out std_logic_vector(3 downto 0);
+ pi_nt_v_mirror : in std_logic;\r
+ \r
+ --for debugging..\r
+ po_dbg_cnt : out std_logic_vector (63 downto 0)\r
);
end de0_cv_nes;
architecture rtl of de0_cv_nes is
component mos6502
- generic ( dsize : integer := 8;
- asize : integer :=16
- );
- port (
- signal dbg_instruction : out std_logic_vector(7 downto 0);
- signal dbg_int_d_bus : out std_logic_vector(7 downto 0);\r
- signal dbg_exec_cycle : out std_logic_vector (5 downto 0);
- signal dbg_ea_carry : out std_logic;
- signal dbg_status : out std_logic_vector(7 downto 0);
- signal dbg_pcl, dbg_pch, dbg_sp, dbg_x, dbg_y, dbg_acc : out std_logic_vector(7 downto 0);
- signal dbg_dec_oe_n : out std_logic;
- signal dbg_dec_val : out std_logic_vector (7 downto 0);
- signal dbg_stat_we_n : out std_logic;
- signal dbg_idl_h, dbg_idl_l : out std_logic_vector (7 downto 0);
-
- cpu_clk : in std_logic; --phi0 input pin.
- dl_cpu_clk : in std_logic; --phi1 delayed clock.
- rdy : in std_logic;
- rst_n : in std_logic;
- irq_n : in std_logic;
- nmi_n : in std_logic;
- r_nw : out std_logic;
- addr : out std_logic_vector ( asize - 1 downto 0);
- d_io : inout std_logic_vector ( dsize - 1 downto 0)
- );
- end component;
-
- component clock_divider
- port ( base_clk : in std_logic;
- reset_n : in std_logic;
- cpu_clk : out std_logic;
- ppu_clk : out std_logic;
- emu_ppu_clk : out std_logic;
- vga_clk : out std_logic;
- cpu_mem_clk : out std_logic;
- cpu_recv_clk : out std_logic;
- emu_ppu_mem_clk : out std_logic
- );
- end component;
-
- component address_decoder
- generic (abus_size : integer := 16; dbus_size : integer := 8);
- port (
- addr : in std_logic_vector (abus_size - 1 downto 0);
- rom_ce_n : out std_logic;
- ram_ce_n : out std_logic;
- ppu_ce_n : out std_logic;
- apu_ce_n : out std_logic
- );
- end component;
-
- component tss_ram
- generic (abus_size : integer := 16; dbus_size : integer := 8);
- port (
- clk : in std_logic;
- ce_n, oe_n, we_n : in std_logic; --select pin active low.
- addr : in std_logic_vector (abus_size - 1 downto 0);
- d_io : inout std_logic_vector (dbus_size - 1 downto 0)
- );
- end component;
-
- component ram
- generic (abus_size : integer := 16; dbus_size : integer := 8);
- port (
- clk : in std_logic;
- ce_n, oe_n, we_n : in std_logic; --select pin active low.
- addr : in std_logic_vector (abus_size - 1 downto 0);
- d_io : inout std_logic_vector (dbus_size - 1 downto 0)
- );
- end component;
-
- component prg_rom
- generic (abus_size : integer := 15; dbus_size : integer := 8);
port (
- clk : in std_logic;
- ce_n : in std_logic; --active low.
- addr : in std_logic_vector (abus_size - 1 downto 0);
- data : out std_logic_vector (dbus_size - 1 downto 0)
+ pi_rst_n : in std_logic;\r
+ pi_base_clk : in std_logic;\r
+ pi_cpu_en : in std_logic_vector (7 downto 0);\r
+ pi_rdy : in std_logic;\r
+ pi_irq_n : in std_logic;\r
+ pi_nmi_n : in std_logic;\r
+ po_r_nw : out std_logic;\r
+ po_addr : out std_logic_vector ( 15 downto 0);\r
+ pio_d_io : inout std_logic_vector ( 7 downto 0)\r
);
end component;
+ component clock_selector\r
+ port (\r
+ pi_rst_n : in std_logic;\r
+ pi_base_clk : in std_logic;\r
+ po_cpu_en : out std_logic_vector (7 downto 0);\r
+ po_rnd_en : out std_logic_vector (3 downto 0)\r
+ );\r
+ end component;\r
+\r
+ component chip_selector\r
+ port (\r
+ pi_rst_n : in std_logic;\r
+ pi_base_clk : in std_logic;\r
+ pi_addr : in std_logic_vector (15 downto 0);\r
+ po_rom_ce_n : out std_logic;\r
+ po_ram_ce_n : out std_logic;\r
+ po_ppu_ce_n : out std_logic;\r
+ po_apu_ce_n : out std_logic\r
+ );\r
+ end component;\r
+\r
+ component prg_rom port (\r
+ pi_base_clk : in std_logic;\r
+ pi_ce_n : in std_logic;\r
+ pi_addr : in std_logic_vector (14 downto 0);\r
+ po_data : out std_logic_vector (7 downto 0)\r
+ );\r
+ end component;\r
+\r
component ppu port (
- signal dbg_ppu_ce_n : out std_logic;
- signal dbg_ppu_ctrl, dbg_ppu_mask, dbg_ppu_status : out std_logic_vector (7 downto 0);
- signal dbg_ppu_addr : out std_logic_vector (13 downto 0);
- signal dbg_ppu_data, dbg_ppu_scrl_x, dbg_ppu_scrl_y : out std_logic_vector (7 downto 0);
-
- signal dbg_nes_x : out std_logic_vector (8 downto 0);
- signal dbg_vga_x : out std_logic_vector (9 downto 0);
- signal dbg_nes_y : out std_logic_vector (8 downto 0);
- signal dbg_vga_y : out std_logic_vector (9 downto 0);
- signal dbg_disp_nt, dbg_disp_attr : out std_logic_vector (7 downto 0);
- signal dbg_disp_ptn_h, dbg_disp_ptn_l : out std_logic_vector (15 downto 0);
- signal dbg_plt_ce_rn_wn : out std_logic_vector (2 downto 0);
- signal dbg_plt_addr : out std_logic_vector (4 downto 0);
- signal dbg_plt_data : out std_logic_vector (7 downto 0);
- signal dbg_p_oam_ce_rn_wn : out std_logic_vector (2 downto 0);
- signal dbg_p_oam_addr : out std_logic_vector (7 downto 0);
- signal dbg_p_oam_data : out std_logic_vector (7 downto 0);
- signal dbg_s_oam_ce_rn_wn : out std_logic_vector (2 downto 0);
- signal dbg_s_oam_addr : out std_logic_vector (4 downto 0);
- signal dbg_s_oam_data : out std_logic_vector (7 downto 0);
- signal dbg_s_oam_addr_cpy : out std_logic_vector (4 downto 0);
-
- cpu_clk : in std_logic;
- dl_cpu_clk : in std_logic;
- ppu_clk : in std_logic;
- vga_clk : in std_logic;
- emu_ppu_clk : in std_logic;
- emu_ppu_clk_dl : in std_logic;
- ce_n : in std_logic;
- rst_n : in std_logic;
- r_nw : in std_logic;
- cpu_addr : in std_logic_vector (2 downto 0);
- cpu_d : inout std_logic_vector (7 downto 0);
-
- vblank_n : out std_logic;
- rd_n : out std_logic;
- wr_n : out std_logic;
- ale_n : out std_logic;
- vram_addr : out std_logic_vector (13 downto 0);
- vram_data : inout std_logic_vector (7 downto 0);
-
- h_sync_n : out std_logic;
- v_sync_n : out std_logic;
- r : out std_logic_vector(3 downto 0);
- g : out std_logic_vector(3 downto 0);
- b : out std_logic_vector(3 downto 0)
+ pi_rst_n : in std_logic;\r
+ pi_base_clk : in std_logic;
+ pi_cpu_en : in std_logic_vector (7 downto 0);\r
+ pi_ce_n : in std_logic;
+ pi_r_nw : in std_logic;
+ pi_cpu_addr : in std_logic_vector (2 downto 0);
+ pio_cpu_d : inout std_logic_vector (7 downto 0);
+
+ po_v_ce_n : out std_logic;\r
+ po_v_rd_n : out std_logic;\r
+ po_v_wr_n : out std_logic;\r
+ po_v_addr : out std_logic_vector (13 downto 0);\r
+ pio_v_data : inout std_logic_vector (7 downto 0);\r
+\r
+ po_plt_ce_n : out std_logic;\r
+ po_plt_rd_n : out std_logic;\r
+ po_plt_wr_n : out std_logic;\r
+ po_plt_addr : out std_logic_vector (4 downto 0);\r
+ pio_plt_data : inout std_logic_vector (7 downto 0);\r
+\r
+ po_spr_ce_n : out std_logic;\r
+ po_spr_rd_n : out std_logic;\r
+ po_spr_wr_n : out std_logic;\r
+ po_spr_addr : out std_logic_vector (7 downto 0);\r
+ po_spr_data : out std_logic_vector (7 downto 0);\r
+\r
+ po_ppu_ctrl : out std_logic_vector (7 downto 0);\r
+ po_ppu_mask : out std_logic_vector (7 downto 0);\r
+ pi_ppu_status : in std_logic_vector (7 downto 0);\r
+ po_ppu_scroll_x : out std_logic_vector (7 downto 0);\r
+ po_ppu_scroll_y : out std_logic_vector (7 downto 0)\r
);
end component;
- component v_address_decoder
- generic (abus_size : integer := 14; dbus_size : integer := 8);
- port (
- v_addr : in std_logic_vector (13 downto 0);
- nt_v_mirror : in std_logic;
- pt_ce_n : out std_logic;
- nt0_ce_n : out std_logic;
- nt1_ce_n : out std_logic
- );
- end component;
-
- component chr_rom
- generic (abus_size : integer := 13; dbus_size : integer := 8);
- port (
- clk : in std_logic;
- ce_n : in std_logic; --active low.
- addr : in std_logic_vector (abus_size - 1 downto 0);
- data : out std_logic_vector (dbus_size - 1 downto 0)\r
- );
- end component;
-
- component d_flip_flop
- generic (
- dsize : integer := 8
- );
- port ( clk : in std_logic;
- res_n : in std_logic;
- set_n : in std_logic;
- we_n : in std_logic;
- d : in std_logic_vector (dsize - 1 downto 0);
- q : out std_logic_vector (dsize - 1 downto 0)
- );
- end component;
-
- component apu
- port ( clk : in std_logic;
- ce_n : in std_logic;
- rst_n : in std_logic;
- r_nw : inout std_logic;
- cpu_addr : inout std_logic_vector (15 downto 0);
- cpu_d : inout std_logic_vector (7 downto 0);
- rdy : out std_logic
- );
- end component;
+ component ram\r
+ generic (abus_size : integer := 16; dbus_size : integer := 8);\r
+ port (\r
+ pi_base_clk : in std_logic;\r
+ pi_ce_n : in std_logic;\r
+ pi_oe_n : in std_logic;\r
+ pi_we_n : in std_logic;\r
+ pi_addr : in std_logic_vector (abus_size - 1 downto 0);\r
+ pio_d_io : inout std_logic_vector (dbus_size - 1 downto 0)\r
+ );\r
+ end component;\r
\r
- constant data_size : integer := 8;
- constant addr_size : integer := 16;
- constant vram_size14 : integer := 14;
-
- constant ram_2k : integer := 11; --2k = 11 bit width.
- constant rom_32k : integer := 15; --32k = 15 bit width.
- constant rom_8k : integer := 13; --8k = 13 bit width. (for test use)
- constant vram_1k : integer := 10; --1k = 10 bit width.
- constant chr_rom_8k : integer := 13; --32k = 15 bit width.
-
- signal cpu_clk : std_logic;
- signal ppu_clk : std_logic;
- signal vga_clk : std_logic;
- signal emu_ppu_clk : std_logic;
- signal cpu_mem_clk : std_logic;
- signal cpu_recv_clk : std_logic;
- signal emu_ppu_mem_clk : std_logic;
-
- signal rdy, irq_n, nmi_n, r_nw : std_logic;
- signal addr : std_logic_vector( addr_size - 1 downto 0);
- signal d_io : std_logic_vector( data_size - 1 downto 0);
-
- signal rom_ce_n : std_logic;
- signal ram_ce_n : std_logic;
- signal ram_oe_n : std_logic;
- signal ppu_ce_n : std_logic;
- signal apu_ce_n : std_logic;
-
- signal rd_n : std_logic;
- signal wr_n : std_logic;
- signal ale_n : std_logic;
- signal v_addr : std_logic_vector (13 downto 0);
- signal v_addr_ppu : std_logic_vector (13 downto 0);
- signal v_data : std_logic_vector (7 downto 0);
- signal pt_ce_n : std_logic;
- signal nt0_ce_n : std_logic;
- signal nt1_ce_n : std_logic;
-
- signal dbg_pcl, dbg_pch : std_logic_vector(7 downto 0);
- signal dbg_stat_we_n : std_logic;
- signal dbg_idl_h, dbg_idl_l : std_logic_vector (7 downto 0);
-
- signal dbg_vga_clk : std_logic;
- signal dbg_ppu_addr_dummy : std_logic_vector (13 downto 0);
- signal dbg_nes_x : std_logic_vector (8 downto 0);
- signal dbg_vga_x : std_logic_vector (9 downto 0);
- signal dbg_nes_y : std_logic_vector (8 downto 0);
- signal dbg_vga_y : std_logic_vector (9 downto 0);
- signal dbg_plt_ce_rn_wn : std_logic_vector (2 downto 0);
- signal dbg_plt_addr : std_logic_vector (4 downto 0);
- signal dbg_plt_data : std_logic_vector (7 downto 0);
- signal dbg_p_oam_ce_rn_wn : std_logic_vector (2 downto 0);
- signal dbg_p_oam_addr : std_logic_vector (7 downto 0);
- signal dbg_p_oam_data : std_logic_vector (7 downto 0);
- signal dbg_s_oam_ce_rn_wn : std_logic_vector (2 downto 0);
- signal dbg_s_oam_addr : std_logic_vector (4 downto 0);
- signal dbg_s_oam_data : std_logic_vector (7 downto 0);
- signal dbg_s_oam_addr_cpy : std_logic_vector (4 downto 0);
- signal dbg_ppu_ctrl_dummy : std_logic_vector (7 downto 0);\r
- signal dbg_ppu_mask_dummy : std_logic_vector (7 downto 0);\r
- signal dbg_ppu_data_dummy : std_logic_vector (7 downto 0);\r
- signal dbg_ppu_status_dummy : std_logic_vector (7 downto 0);
- signal dbg_ppu_scrl_x_dummy : std_logic_vector (7 downto 0);
- signal dbg_ppu_scrl_y_dummy : std_logic_vector (7 downto 0);
- signal dbg_disp_ptn_h_dummy, dbg_disp_ptn_l_dummy : std_logic_vector (15 downto 0);
-
- signal dbg_instruction_dummy : std_logic_vector(7 downto 0);
- signal dbg_int_d_bus_dummy : std_logic_vector(7 downto 0);\r
- signal dbg_exec_cycle_dummy : std_logic_vector (5 downto 0);
- signal dbg_ea_carry_dummy : std_logic;
- signal dbg_status_dummy : std_logic_vector(7 downto 0);
- signal dbg_sp_dummy, dbg_x_dummy, dbg_y_dummy, dbg_acc_dummy : std_logic_vector(7 downto 0);\r
- signal dbg_dec_oe_n : std_logic;\r
- signal dbg_dec_val : std_logic_vector (7 downto 0);\r
- signal dbg_int_d_bus : std_logic_vector(7 downto 0);\r
- signal dbg_sp, dbg_x, dbg_y, dbg_acc : std_logic_vector(7 downto 0);\r
- signal dbg_disp_nt, dbg_disp_attr : std_logic_vector (7 downto 0);\r
- signal dbg_disp_ptn_h, dbg_disp_ptn_l : std_logic_vector (15 downto 0);\r
-
+ component palette_ram\r
+ port (\r
+ pi_base_clk : in std_logic;\r
+ pi_ce_n : in std_logic;\r
+ pi_oe_n : in std_logic;\r
+ pi_we_n : in std_logic;\r
+ pi_addr : in std_logic_vector (4 downto 0);\r
+ pio_d_io : inout std_logic_vector (7 downto 0)\r
+ );\r
+ end component;\r
+\r
+ component chr_rom\r
+ port ( \r
+ pi_base_clk : in std_logic;\r
+ pi_ce_n : in std_logic;\r
+ pi_addr : in std_logic_vector (12 downto 0);\r
+ po_data : out std_logic_vector (7 downto 0)\r
+ );\r
+ end component;\r
+\r
+ component v_chip_selector\r
+ port (\r
+ pi_rst_n : in std_logic;\r
+ pi_base_clk : in std_logic;\r
+ pi_v_ce_n : in std_logic;\r
+ pi_v_addr : in std_logic_vector (13 downto 0);\r
+ pi_nt_v_mirror : in std_logic;\r
+ po_pt_ce_n : out std_logic;\r
+ po_nt0_ce_n : out std_logic;\r
+ po_nt1_ce_n : out std_logic\r
+ );\r
+ end component;\r
+\r
+ component render\r
+ port (\r
+ pi_rst_n : in std_logic;\r
+ pi_base_clk : in std_logic;\r
+ pi_rnd_en : in std_logic_vector (3 downto 0);\r
+\r
+ --ppu i/f\r
+ pi_ppu_ctrl : in std_logic_vector (7 downto 0);\r
+ pi_ppu_mask : in std_logic_vector (7 downto 0);\r
+ po_ppu_status : out std_logic_vector (7 downto 0);\r
+ pi_ppu_scroll_x : in std_logic_vector (7 downto 0);\r
+ pi_ppu_scroll_y : in std_logic_vector (7 downto 0);\r
\r
- component counter_register \r
- generic (\r
- dsize : integer := 8;\r
- inc : integer := 1\r
- );\r
- port ( clk : in std_logic;\r
- rst_n : in std_logic;\r
- ce_n : in std_logic;\r
- we_n : in std_logic;\r
- d : in std_logic_vector(dsize - 1 downto 0);\r
- q : out std_logic_vector(dsize - 1 downto 0)\r
- );\r
+ --vram i/f\r
+ po_v_ce_n : out std_logic;\r
+ po_v_rd_n : out std_logic;\r
+ po_v_wr_n : out std_logic;\r
+ po_v_addr : out std_logic_vector (13 downto 0);\r
+ pi_v_data : in std_logic_vector (7 downto 0);\r
+\r
+ --plt i/f\r
+ po_plt_ce_n : out std_logic;\r
+ po_plt_rd_n : out std_logic;\r
+ po_plt_wr_n : out std_logic;\r
+ po_plt_addr : out std_logic_vector (4 downto 0);\r
+ pi_plt_data : in std_logic_vector (7 downto 0);\r
+\r
+ --sprite i/f\r
+ po_spr_ce_n : out std_logic;\r
+ po_spr_rd_n : out std_logic;\r
+ po_spr_wr_n : out std_logic;\r
+ po_spr_addr : out std_logic_vector (7 downto 0);\r
+ pi_spr_data : in std_logic_vector (7 downto 0);\r
+\r
+ --vga output\r
+ po_h_sync_n : out std_logic;\r
+ po_v_sync_n : out std_logic;\r
+ po_r : out std_logic_vector(3 downto 0);\r
+ po_g : out std_logic_vector(3 downto 0);\r
+ po_b : out std_logic_vector(3 downto 0)\r
+ );\r
end component;\r
- signal loop24 : std_logic_vector (23 downto 0);\r
- signal clock_counter : std_logic_vector (63 downto 0);\r
+\r
+constant ram_2k : integer := 11; --2k = 11 bit width.\r
+constant rom_32k : integer := 15; --32k = 15 bit width.\r
+constant vram_1k : integer := 10; --1k = 10 bit width.\r
+\r
+signal wr_cpu_en : std_logic_vector (7 downto 0);\r
+signal wr_rnd_en : std_logic_vector (3 downto 0);\r
+\r
+signal wr_rdy : std_logic;\r
+signal wr_irq_n : std_logic;\r
+signal wr_nmi_n : std_logic;\r
+signal wr_r_nw : std_logic;\r
+--r_n is negative logic of wr_r_nw.\r
+signal lg_r_n : std_logic;\r
+\r
+signal wr_addr : std_logic_vector ( 15 downto 0);\r
+signal wr_d_io : std_logic_vector ( 7 downto 0);\r
+\r
+signal wr_rom_ce_n : std_logic;\r
+signal wr_ram_ce_n : std_logic;\r
+signal wr_ppu_ce_n : std_logic;\r
+signal wr_apu_ce_n : std_logic;\r
+\r
+signal wr_v_ce_n : std_logic;\r
+signal wr_v_rd_n : std_logic;\r
+signal wr_v_wr_n : std_logic;\r
+signal wr_v_addr : std_logic_vector (13 downto 0);\r
+signal wr_v_data : std_logic_vector (7 downto 0);\r
+\r
+signal wr_plt_ce_n : std_logic;\r
+signal wr_plt_rd_n : std_logic;\r
+signal wr_plt_wr_n : std_logic;\r
+signal wr_plt_addr : std_logic_vector (4 downto 0);\r
+signal wr_plt_data : std_logic_vector (7 downto 0);\r
+\r
+signal wr_spr_ce_n : std_logic;\r
+signal wr_spr_rd_n : std_logic;\r
+signal wr_spr_wr_n : std_logic;\r
+signal wr_spr_addr : std_logic_vector (7 downto 0);\r
+signal wr_spr_data : std_logic_vector (7 downto 0);\r
+\r
+signal wr_pt_ce_n : std_logic;\r
+signal wr_nt0_ce_n : std_logic;\r
+signal wr_nt1_ce_n : std_logic;\r
+\r
+signal wr_ppu_ctrl : std_logic_vector (7 downto 0);\r
+signal wr_ppu_mask : std_logic_vector (7 downto 0);\r
+signal wr_ppu_status : std_logic_vector (7 downto 0);\r
+signal wr_ppu_scroll_x : std_logic_vector (7 downto 0);\r
+signal wr_ppu_scroll_y : std_logic_vector (7 downto 0);\r
+\r
+signal reg_dbg_cnt : std_logic_vector (63 downto 0);\r
\r
begin
-
- irq_n <= '0';
-
- --ppu/cpu clock generator
- clock_inst : clock_divider port map
- (base_clk, rst_n, cpu_clk, ppu_clk, emu_ppu_clk, vga_clk, cpu_mem_clk, cpu_recv_clk, emu_ppu_mem_clk);
-
- addr_dec_inst : address_decoder generic map (addr_size, data_size) \r
- port map (addr, rom_ce_n, ram_ce_n, ppu_ce_n, apu_ce_n);\r
-\r
- --mos 6502 cpu instance
- cpu_inst : mos6502 generic map (data_size, addr_size)
- port map (
- dbg_instruction,
- dbg_int_d_bus,\r
- dbg_exec_cycle,
- dbg_ea_carry,
- dbg_status,
- dbg_pcl, dbg_pch, dbg_sp, dbg_x, dbg_y, dbg_acc,\r
- dbg_dec_oe_n,\r
- dbg_dec_val,\r
- dbg_stat_we_n ,
- dbg_idl_h, dbg_idl_l,
-
- cpu_clk, cpu_recv_clk, rdy,
- rst_n, irq_n, nmi_n, r_nw,
- addr, d_io);
-
- --main ROM/RAM instance
- prg_rom_inst : prg_rom generic map (rom_32k, data_size)
- port map (cpu_mem_clk, rom_ce_n, addr(rom_32k - 1 downto 0), d_io);
-
- ram_oe_n <= not R_nW;
- prg_ram_inst : tss_ram generic map (ram_2k, data_size)
- port map (cpu_mem_clk, ram_ce_n, ram_oe_n, R_nW, addr(ram_2k - 1 downto 0), d_io);
-\r
- --nes ppu instance
- ppu_inst: ppu port map (
- dbg_ppu_ce_n ,
- dbg_ppu_ctrl_dummy, dbg_ppu_mask_dummy, dbg_ppu_status ,
- dbg_ppu_addr ,
- dbg_ppu_data_dummy, dbg_ppu_scrl_x, dbg_ppu_scrl_y ,
-
- dbg_nes_x ,
- dbg_vga_x ,
- dbg_nes_y ,
- dbg_vga_y ,
- dbg_disp_nt, dbg_disp_attr ,
- dbg_disp_ptn_h, dbg_disp_ptn_l ,
- dbg_plt_ce_rn_wn ,
- dbg_plt_addr ,
- dbg_plt_data ,
- dbg_p_oam_ce_rn_wn ,
- dbg_p_oam_addr ,
- dbg_p_oam_data ,
- dbg_s_oam_ce_rn_wn ,
- dbg_s_oam_addr ,
- dbg_s_oam_data ,
- dbg_s_oam_addr_cpy ,
-
- cpu_clk ,
- cpu_mem_clk ,
- ppu_clk ,
- vga_clk ,
- emu_ppu_clk ,
- emu_ppu_mem_clk ,
- ppu_ce_n ,
- rst_n ,
- r_nw ,
- addr(2 downto 0) ,
- d_io ,
-
- nmi_n ,
- rd_n ,
- wr_n ,
- ale_n ,
- v_addr_ppu ,
- v_data ,
-
- h_sync_n ,
- v_sync_n ,
- r ,
- g ,
- b
-
- );
-
- ppu_addr_decoder : v_address_decoder generic map (vram_size14, data_size)
- port map (v_addr, nt_v_mirror, pt_ce_n, nt0_ce_n, nt1_ce_n);
-
- --transparent d-latch
- --ale_n=0 >> addr latch\r
- --ale_n=1 >> addr output.\r
- vram_latch : d_flip_flop generic map (vram_size14)
- port map(emu_ppu_mem_clk, rst_n, '1', ale_n, v_addr_ppu, v_addr);
-
- vchr_rom : chr_rom generic map (chr_rom_8k, data_size)
- port map (emu_ppu_mem_clk, pt_ce_n, v_addr(chr_rom_8k - 1 downto 0), v_data);
-
- --name table/attr table
- vram_nt0 : ram generic map (vram_1k, data_size)
- port map (emu_ppu_mem_clk, nt0_ce_n, rd_n, wr_n, v_addr(vram_1k - 1 downto 0), v_data);
-
- vram_nt1 : ram generic map (vram_1k, data_size)
- port map (emu_ppu_mem_clk, nt1_ce_n, rd_n, wr_n, v_addr(vram_1k - 1 downto 0), v_data);
-
- --APU/DMA instance
- apu_inst : apu
- port map (cpu_clk, apu_ce_n, rst_n, r_nw, addr, d_io, rdy);
\r
-
-
------------------------------------------------------------\r
------------------------------------------------------------\r
-------------------debug pin setting....-------------------- \r
------------------------------------------------------------\r
------------------------------------------------------------\r
- --for debugging cpu timing, use ppu clock for jtag clock.\r
- dbg_base_clk <= base_clk;\r
-\r
- clock_counter_inst : counter_register generic map (64) port map \r
- (cpu_clk, rst_n, '0', '1', (others=>'0'), clock_counter);\r
-\r
--- led_test : counter_register generic map (24) port map \r
--- (base_clk, rst_n, '0', '1', (others=>'0'), loop24);\r
--- dbg_cpu_clk <= loop24(23);\r
--- dbg_ppu_clk <= loop24(22);\r
--- dbg_mem_clk <= loop24(21);\r
-\r
-\r
- ----general...\r
- dbg_cpu_clk <= cpu_clk;\r
- dbg_ppu_clk <= ppu_clk;\r
- dbg_emu_ppu_clk <= emu_ppu_clk;\r
- dbg_cpu_mem_clk <= cpu_mem_clk;\r
- dbg_vga_clk <= vga_clk;
- dbg_r_nw <= r_nw;\r
- dbg_addr <= addr;\r
- dbg_d_io <= d_io;\r
- dbg_v_addr <= v_addr;\r
- dbg_v_data <= v_data;\r
- dbg_nmi <= nmi_n;\r
-\r
- ----cpu...\r
- dbg_ppu_ctrl <= dbg_pcl;\r
- dbg_ppu_data <= dbg_idl_l;\r
- dbg_ppu_mask <= dbg_idl_h;\r
-\r
- --ppu debug....\r
--- dbg_exec_cycle(0) <= dbg_nes_x(8);\r
--- dbg_instruction <= dbg_nes_x(7 downto 0);\r
--- dbg_exec_cycle(4) <= dbg_nes_y(8);\r
--- dbg_status <= dbg_nes_y(7 downto 0);\r
---\r
--- dbg_disp_ptn_l (7 downto 0) <= dbg_p_oam_addr;\r
--- dbg_disp_ptn_l (15 downto 8) <= dbg_p_oam_data;\r
--- dbg_int_d_bus(4 downto 0) <= dbg_s_oam_addr(4 downto 0);
--- --dbg_ppu_scrl_y <= dbg_s_oam_data;
--- dbg_ppu_scrl_y <= dbg_ppu_scrl_y_dummy;
---\r
--- dbg_ppu_scrl_x(0) <= ale_n;
--- dbg_ppu_scrl_x(1) <= rd_n;
--- dbg_ppu_scrl_x(2) <= wr_n;
--- dbg_ppu_scrl_x(3) <= nt0_ce_n;
-
- --nmi_n <= dummy_nmi;
- ---------------
+ dbg_base_clk <= pi_base_clk;\r
+\r
+ --synchronized clock generator instance\r
+ clock_selector_inst : clock_selector port map (\r
+ pi_rst_n,\r
+ pi_base_clk,\r
+ wr_cpu_en,\r
+ wr_rnd_en\r
+ );\r
+\r
+ --mos 6502 cpu instance\r
+ cpu_inst : mos6502 port map (\r
+ pi_rst_n, \r
+ pi_base_clk, \r
+ wr_cpu_en, \r
+ wr_rdy,\r
+ wr_irq_n, \r
+ wr_nmi_n, \r
+ wr_r_nw, \r
+ wr_addr, \r
+ wr_d_io\r
+ );\r
+\r
+ --chip select (address decode)\r
+ cs_inst : chip_selector port map (\r
+ pi_rst_n,\r
+ pi_base_clk, \r
+ wr_addr,\r
+ wr_rom_ce_n,\r
+ wr_ram_ce_n,\r
+ wr_ppu_ce_n,\r
+ wr_apu_ce_n\r
+ );\r
+\r
+ --program rom\r
+ prom_inst : prg_rom port map (\r
+ pi_base_clk, \r
+ wr_rom_ce_n,\r
+ wr_addr(14 downto 0), \r
+ wr_d_io\r
+ );\r
+\r
+ lg_r_n <= not wr_r_nw;\r
+ --cpu ram inst.\r
+ cpu_ram_inst : ram generic map\r
+ (ram_2k, 8) port map (\r
+ pi_base_clk,\r
+ wr_ram_ce_n,\r
+ lg_r_n, \r
+ wr_r_nw, \r
+ wr_addr(10 downto 0), \r
+ wr_d_io\r
+ );\r
+\r
+ --ppu\r
+ ppu_inst : ppu port map (\r
+ pi_rst_n, \r
+ pi_base_clk, \r
+ wr_cpu_en,\r
+ wr_ppu_ce_n,\r
+ wr_r_nw, \r
+ wr_addr(2 downto 0), \r
+ wr_d_io,\r
+\r
+ wr_v_ce_n,\r
+ wr_v_rd_n,\r
+ wr_v_wr_n,\r
+ wr_v_addr,\r
+ wr_v_data,\r
+\r
+ wr_plt_ce_n,\r
+ wr_plt_rd_n,\r
+ wr_plt_wr_n,\r
+ wr_plt_addr,\r
+ wr_plt_data,\r
+\r
+ wr_spr_ce_n,\r
+ wr_spr_rd_n,\r
+ wr_spr_wr_n,\r
+ wr_spr_addr,\r
+ wr_spr_data,\r
+\r
+ --render i/f\r
+ wr_ppu_ctrl,\r
+ wr_ppu_mask,\r
+ wr_ppu_status,\r
+ wr_ppu_scroll_x,\r
+ wr_ppu_scroll_y\r
+ );\r
\r
+ --vram chip select (address decode)\r
+ vcs_inst : v_chip_selector port map (\r
+ pi_rst_n,\r
+ pi_base_clk,\r
+ wr_v_ce_n,\r
+ wr_v_addr,\r
+ pi_nt_v_mirror,\r
+ wr_pt_ce_n,\r
+ wr_nt0_ce_n,\r
+ wr_nt1_ce_n\r
+ );\r
+\r
+ --name table/attr table #0\r
+ vram_nt0_inst : ram generic map\r
+ (vram_1k, 8) port map (\r
+ pi_base_clk,\r
+ wr_nt0_ce_n,\r
+ wr_v_rd_n,\r
+ wr_v_wr_n,\r
+ wr_v_addr(vram_1k - 1 downto 0),\r
+ wr_v_data\r
+ );\r
+\r
+ --name table/attr table #1\r
+ vram_nt1_inst : ram generic map\r
+ (vram_1k, 8) port map (\r
+ pi_base_clk,\r
+ wr_nt1_ce_n,\r
+ wr_v_rd_n,\r
+ wr_v_wr_n,\r
+ wr_v_addr(vram_1k - 1 downto 0),\r
+ wr_v_data\r
+ );\r
+\r
+ --palette table\r
+ vram_plt_inst : palette_ram port map (\r
+ pi_base_clk,\r
+ wr_plt_ce_n,\r
+ wr_plt_rd_n,\r
+ wr_plt_wr_n,\r
+ wr_plt_addr,\r
+ wr_plt_data\r
+ );\r
+\r
+ --pattern table\r
+ chr_rom_inst : chr_rom port map (\r
+ pi_base_clk,\r
+ wr_pt_ce_n,\r
+ wr_v_addr(12 downto 0),\r
+ wr_v_data\r
+ );\r
+\r
+ --palette table\r
+ spr_ram_inst : ram generic map\r
+ (8, 8) port map (\r
+ pi_base_clk,\r
+ wr_spr_ce_n,\r
+ wr_spr_rd_n,\r
+ wr_spr_wr_n,\r
+ wr_spr_addr,\r
+ wr_spr_data\r
+ );\r
+\r
+ --vga render instance\r
+ render_inst : render port map (\r
+ pi_rst_n, \r
+ pi_base_clk,\r
+ wr_rnd_en,\r
+\r
+ --ppu i/f\r
+ wr_ppu_ctrl,\r
+ wr_ppu_mask,\r
+ wr_ppu_status,\r
+ wr_ppu_scroll_x,\r
+ wr_ppu_scroll_y,\r
+\r
+ --vram i/f\r
+ wr_v_ce_n,\r
+ wr_v_rd_n,\r
+ wr_v_wr_n,\r
+ wr_v_addr,\r
+ wr_v_data,\r
+\r
+ --plt i/f\r
+ wr_plt_ce_n,\r
+ wr_plt_rd_n,\r
+ wr_plt_wr_n,\r
+ wr_plt_addr,\r
+ wr_plt_data,\r
+\r
+ --sprite i/f\r
+ wr_spr_ce_n,\r
+ wr_spr_rd_n,\r
+ wr_spr_wr_n,\r
+ wr_spr_addr,\r
+ wr_spr_data,\r
+\r
+ --vga output\r
+ po_h_sync_n,\r
+ po_v_sync_n,\r
+ po_r,\r
+ po_g,\r
+ po_b\r
+ );\r
+\r
+ wr_rdy <= '1';\r
+ wr_irq_n <= '1';\r
+ wr_nmi_n <= '1';\r
+\r
+ po_dbg_cnt <= reg_dbg_cnt;\r
+ deb_cnt_p : process (pi_rst_n, pi_base_clk)\r
+use ieee.std_logic_unsigned.all;\r
+ variable cnt : integer;\r
+ begin\r
+ if (pi_rst_n = '0') then\r
+ reg_dbg_cnt <= (others => '0');\r
+ cnt := 0;\r
+ else\r
+ if (rising_edge(pi_base_clk)) then\r
+ if (cnt = 0) then\r
+ --debug count is half cycle because too fast to capture in st ii.\r
+ reg_dbg_cnt <= reg_dbg_cnt + 1;\r
+ cnt := 1;\r
+ else\r
+ cnt := 0;\r
+ end if;\r
+ end if;\r
+ end if;\r
+ end process;\r
end rtl;
-
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