po_r : out std_logic_vector(3 downto 0);
po_g : out std_logic_vector(3 downto 0);
po_b : out std_logic_vector(3 downto 0);
- pi_nt_v_mirror : in std_logic\r
+ pi_nt_v_mirror : in std_logic;\r
+ \r
+ --for debugging..\r
+ po_dbg_cnt : out std_logic_vector (63 downto 0)\r
);
end de0_cv_nes;
);\r
end component;\r
\r
+ component prg_rom port (\r
+ pi_base_clk : in std_logic;\r
+ pi_ce_n : in std_logic;\r
+ pi_addr : in std_logic_vector (14 downto 0);\r
+ po_data : out std_logic_vector (7 downto 0)\r
+ );\r
+ end component;\r
+\r
component ppu port (
pi_rst_n : in std_logic;\r
pi_base_clk : in std_logic;
signal wr_irq_n : std_logic;\r
signal wr_nmi_n : std_logic;\r
signal wr_r_nw : std_logic;\r
+--r_n is negative logic of wr_r_nw.\r
+signal lg_r_n : std_logic;\r
\r
signal wr_addr : std_logic_vector ( 15 downto 0);\r
signal wr_d_io : std_logic_vector ( 7 downto 0);\r
signal wr_ppu_scroll_x : std_logic_vector (7 downto 0);\r
signal wr_ppu_scroll_y : std_logic_vector (7 downto 0);\r
\r
+signal reg_dbg_cnt : std_logic_vector (63 downto 0);\r
+\r
begin
\r
dbg_base_clk <= pi_base_clk;\r
wr_apu_ce_n\r
);\r
\r
+ --program rom\r
+ prom_inst : prg_rom port map (\r
+ pi_base_clk, \r
+ wr_rom_ce_n,\r
+ wr_addr(14 downto 0), \r
+ wr_d_io\r
+ );\r
+\r
+ lg_r_n <= not wr_r_nw;\r
+ --cpu ram inst.\r
+ cpu_ram_inst : ram generic map\r
+ (ram_2k, 8) port map (\r
+ pi_base_clk,\r
+ wr_ram_ce_n,\r
+ lg_r_n, \r
+ wr_r_nw, \r
+ wr_addr(10 downto 0), \r
+ wr_d_io\r
+ );\r
+\r
--ppu\r
ppu_inst : ppu port map (\r
pi_rst_n, \r
wr_irq_n <= '1';\r
wr_nmi_n <= '1';\r
\r
+ po_dbg_cnt <= reg_dbg_cnt;\r
+ deb_cnt_p : process (pi_rst_n, pi_base_clk)\r
+use ieee.std_logic_unsigned.all;\r
+ variable cnt : integer;\r
+ begin\r
+ if (pi_rst_n = '0') then\r
+ reg_dbg_cnt <= (others => '0');\r
+ cnt := 0;\r
+ else\r
+ if (rising_edge(pi_base_clk)) then\r
+ if (cnt = 0) then\r
+ --debug count is half cycle because too fast to capture in st ii.\r
+ reg_dbg_cnt <= reg_dbg_cnt + 1;\r
+ cnt := 1;\r
+ else\r
+ cnt := 0;\r
+ end if;\r
+ end if;\r
+ end if;\r
+ end process;\r
end rtl;