po_r : out std_logic_vector(3 downto 0);
po_g : out std_logic_vector(3 downto 0);
po_b : out std_logic_vector(3 downto 0);
- pi_nt_v_mirror : in std_logic\r
+ pi_nt_v_mirror : in std_logic;\r
+ \r
+ --for debugging..\r
+ po_dbg_cnt : out std_logic_vector (63 downto 0)\r
);
end de0_cv_nes;
pi_rst_n : in std_logic;\r
pi_base_clk : in std_logic;\r
po_cpu_en : out std_logic_vector (7 downto 0);\r
- po_ppu_en : out std_logic_vector (3 downto 0)\r
+ po_rnd_en : out std_logic_vector (3 downto 0)\r
);\r
end component;\r
\r
);\r
end component;\r
\r
+ component prg_rom port (\r
+ pi_base_clk : in std_logic;\r
+ pi_ce_n : in std_logic;\r
+ pi_addr : in std_logic_vector (14 downto 0);\r
+ po_data : out std_logic_vector (7 downto 0)\r
+ );\r
+ end component;\r
+\r
component ppu port (
pi_rst_n : in std_logic;\r
pi_base_clk : in std_logic;
pi_cpu_addr : in std_logic_vector (2 downto 0);
pio_cpu_d : inout std_logic_vector (7 downto 0);
- po_rd_n : out std_logic;
- po_wr_n : out std_logic;
- po_vram_addr : out std_logic_vector (13 downto 0);
- pio_vram_data : inout std_logic_vector (7 downto 0)
+ po_v_ce_n : out std_logic;\r
+ po_v_rd_n : out std_logic;\r
+ po_v_wr_n : out std_logic;\r
+ po_v_addr : out std_logic_vector (13 downto 0);\r
+ pio_v_data : inout std_logic_vector (7 downto 0);\r
+\r
+ po_plt_ce_n : out std_logic;\r
+ po_plt_rd_n : out std_logic;\r
+ po_plt_wr_n : out std_logic;\r
+ po_plt_addr : out std_logic_vector (4 downto 0);\r
+ pio_plt_data : inout std_logic_vector (7 downto 0);\r
+\r
+ po_spr_ce_n : out std_logic;\r
+ po_spr_rd_n : out std_logic;\r
+ po_spr_wr_n : out std_logic;\r
+ po_spr_addr : out std_logic_vector (7 downto 0);\r
+ po_spr_data : out std_logic_vector (7 downto 0);\r
+\r
+ po_ppu_ctrl : out std_logic_vector (7 downto 0);\r
+ po_ppu_mask : out std_logic_vector (7 downto 0);\r
+ pi_ppu_status : in std_logic_vector (7 downto 0);\r
+ po_ppu_scroll_x : out std_logic_vector (7 downto 0);\r
+ po_ppu_scroll_y : out std_logic_vector (7 downto 0)\r
);
end component;
port (\r
pi_rst_n : in std_logic;\r
pi_base_clk : in std_logic;\r
+ pi_v_ce_n : in std_logic;\r
pi_v_addr : in std_logic_vector (13 downto 0);\r
pi_nt_v_mirror : in std_logic;\r
po_pt_ce_n : out std_logic;\r
po_nt0_ce_n : out std_logic;\r
- po_nt1_ce_n : out std_logic;\r
- po_plt_ce_n : out std_logic\r
+ po_nt1_ce_n : out std_logic\r
+ );\r
+ end component;\r
+\r
+ component render\r
+ port (\r
+ pi_rst_n : in std_logic;\r
+ pi_base_clk : in std_logic;\r
+ pi_rnd_en : in std_logic_vector (3 downto 0);\r
+\r
+ --ppu i/f\r
+ pi_ppu_ctrl : in std_logic_vector (7 downto 0);\r
+ pi_ppu_mask : in std_logic_vector (7 downto 0);\r
+ po_ppu_status : out std_logic_vector (7 downto 0);\r
+ pi_ppu_scroll_x : in std_logic_vector (7 downto 0);\r
+ pi_ppu_scroll_y : in std_logic_vector (7 downto 0);\r
+\r
+ --vram i/f\r
+ po_v_ce_n : out std_logic;\r
+ po_v_rd_n : out std_logic;\r
+ po_v_wr_n : out std_logic;\r
+ po_v_addr : out std_logic_vector (13 downto 0);\r
+ pi_v_data : in std_logic_vector (7 downto 0);\r
+\r
+ --plt i/f\r
+ po_plt_ce_n : out std_logic;\r
+ po_plt_rd_n : out std_logic;\r
+ po_plt_wr_n : out std_logic;\r
+ po_plt_addr : out std_logic_vector (4 downto 0);\r
+ pi_plt_data : in std_logic_vector (7 downto 0);\r
+\r
+ --sprite i/f\r
+ po_spr_ce_n : out std_logic;\r
+ po_spr_rd_n : out std_logic;\r
+ po_spr_wr_n : out std_logic;\r
+ po_spr_addr : out std_logic_vector (7 downto 0);\r
+ pi_spr_data : in std_logic_vector (7 downto 0);\r
+\r
+ --vga output\r
+ po_h_sync_n : out std_logic;\r
+ po_v_sync_n : out std_logic;\r
+ po_r : out std_logic_vector(3 downto 0);\r
+ po_g : out std_logic_vector(3 downto 0);\r
+ po_b : out std_logic_vector(3 downto 0)\r
);\r
end component;\r
\r
constant vram_1k : integer := 10; --1k = 10 bit width.\r
\r
signal wr_cpu_en : std_logic_vector (7 downto 0);\r
-signal wr_ppu_en : std_logic_vector (3 downto 0);\r
+signal wr_rnd_en : std_logic_vector (3 downto 0);\r
\r
signal wr_rdy : std_logic;\r
signal wr_irq_n : std_logic;\r
signal wr_nmi_n : std_logic;\r
signal wr_r_nw : std_logic;\r
+--r_n is negative logic of wr_r_nw.\r
+signal lg_r_n : std_logic;\r
\r
signal wr_addr : std_logic_vector ( 15 downto 0);\r
signal wr_d_io : std_logic_vector ( 7 downto 0);\r
signal wr_ppu_ce_n : std_logic;\r
signal wr_apu_ce_n : std_logic;\r
\r
+signal wr_v_ce_n : std_logic;\r
signal wr_v_rd_n : std_logic;\r
signal wr_v_wr_n : std_logic;\r
-signal wr_vram_addr : std_logic_vector (13 downto 0);\r
-signal wr_vram_data : std_logic_vector (7 downto 0);\r
+signal wr_v_addr : std_logic_vector (13 downto 0);\r
+signal wr_v_data : std_logic_vector (7 downto 0);\r
+\r
+signal wr_plt_ce_n : std_logic;\r
+signal wr_plt_rd_n : std_logic;\r
+signal wr_plt_wr_n : std_logic;\r
+signal wr_plt_addr : std_logic_vector (4 downto 0);\r
+signal wr_plt_data : std_logic_vector (7 downto 0);\r
+\r
+signal wr_spr_ce_n : std_logic;\r
+signal wr_spr_rd_n : std_logic;\r
+signal wr_spr_wr_n : std_logic;\r
+signal wr_spr_addr : std_logic_vector (7 downto 0);\r
+signal wr_spr_data : std_logic_vector (7 downto 0);\r
\r
signal wr_pt_ce_n : std_logic;\r
signal wr_nt0_ce_n : std_logic;\r
signal wr_nt1_ce_n : std_logic;\r
-signal wr_plt_ce_n : std_logic;\r
\r
+signal wr_ppu_ctrl : std_logic_vector (7 downto 0);\r
+signal wr_ppu_mask : std_logic_vector (7 downto 0);\r
+signal wr_ppu_status : std_logic_vector (7 downto 0);\r
+signal wr_ppu_scroll_x : std_logic_vector (7 downto 0);\r
+signal wr_ppu_scroll_y : std_logic_vector (7 downto 0);\r
+\r
+signal reg_dbg_cnt : std_logic_vector (63 downto 0);\r
\r
begin
\r
pi_rst_n,\r
pi_base_clk,\r
wr_cpu_en,\r
- wr_ppu_en\r
+ wr_rnd_en\r
);\r
\r
--mos 6502 cpu instance\r
wr_apu_ce_n\r
);\r
\r
+ --program rom\r
+ prom_inst : prg_rom port map (\r
+ pi_base_clk, \r
+ wr_rom_ce_n,\r
+ wr_addr(14 downto 0), \r
+ wr_d_io\r
+ );\r
+\r
+ lg_r_n <= not wr_r_nw;\r
+ --cpu ram inst.\r
+ cpu_ram_inst : ram generic map\r
+ (ram_2k, 8) port map (\r
+ pi_base_clk,\r
+ wr_ram_ce_n,\r
+ lg_r_n, \r
+ wr_r_nw, \r
+ wr_addr(10 downto 0), \r
+ wr_d_io\r
+ );\r
+\r
--ppu\r
ppu_inst : ppu port map (\r
pi_rst_n, \r
wr_addr(2 downto 0), \r
wr_d_io,\r
\r
+ wr_v_ce_n,\r
wr_v_rd_n,\r
wr_v_wr_n,\r
- wr_vram_addr,\r
- wr_vram_data\r
+ wr_v_addr,\r
+ wr_v_data,\r
+\r
+ wr_plt_ce_n,\r
+ wr_plt_rd_n,\r
+ wr_plt_wr_n,\r
+ wr_plt_addr,\r
+ wr_plt_data,\r
+\r
+ wr_spr_ce_n,\r
+ wr_spr_rd_n,\r
+ wr_spr_wr_n,\r
+ wr_spr_addr,\r
+ wr_spr_data,\r
+\r
+ --render i/f\r
+ wr_ppu_ctrl,\r
+ wr_ppu_mask,\r
+ wr_ppu_status,\r
+ wr_ppu_scroll_x,\r
+ wr_ppu_scroll_y\r
);\r
\r
--vram chip select (address decode)\r
vcs_inst : v_chip_selector port map (\r
pi_rst_n,\r
- pi_base_clk, \r
- wr_vram_addr,\r
+ pi_base_clk,\r
+ wr_v_ce_n,\r
+ wr_v_addr,\r
pi_nt_v_mirror,\r
wr_pt_ce_n,\r
wr_nt0_ce_n,\r
- wr_nt1_ce_n,\r
- wr_plt_ce_n\r
+ wr_nt1_ce_n\r
);\r
\r
--name table/attr table #0\r
wr_nt0_ce_n,\r
wr_v_rd_n,\r
wr_v_wr_n,\r
- wr_vram_addr(vram_1k - 1 downto 0),\r
- wr_vram_data\r
+ wr_v_addr(vram_1k - 1 downto 0),\r
+ wr_v_data\r
);\r
\r
--name table/attr table #1\r
wr_nt1_ce_n,\r
wr_v_rd_n,\r
wr_v_wr_n,\r
- wr_vram_addr(vram_1k - 1 downto 0),\r
- wr_vram_data\r
+ wr_v_addr(vram_1k - 1 downto 0),\r
+ wr_v_data\r
);\r
\r
--palette table\r
vram_plt_inst : palette_ram port map (\r
pi_base_clk,\r
wr_plt_ce_n,\r
- wr_v_rd_n,\r
- wr_v_wr_n,\r
- wr_vram_addr(4 downto 0),\r
- wr_vram_data\r
+ wr_plt_rd_n,\r
+ wr_plt_wr_n,\r
+ wr_plt_addr,\r
+ wr_plt_data\r
);\r
\r
--pattern table\r
chr_rom_inst : chr_rom port map (\r
pi_base_clk,\r
wr_pt_ce_n,\r
- wr_vram_addr(12 downto 0),\r
- wr_vram_data\r
+ wr_v_addr(12 downto 0),\r
+ wr_v_data\r
+ );\r
+\r
+ --palette table\r
+ spr_ram_inst : ram generic map\r
+ (8, 8) port map (\r
+ pi_base_clk,\r
+ wr_spr_ce_n,\r
+ wr_spr_rd_n,\r
+ wr_spr_wr_n,\r
+ wr_spr_addr,\r
+ wr_spr_data\r
+ );\r
+\r
+ --vga render instance\r
+ render_inst : render port map (\r
+ pi_rst_n, \r
+ pi_base_clk,\r
+ wr_rnd_en,\r
+\r
+ --ppu i/f\r
+ wr_ppu_ctrl,\r
+ wr_ppu_mask,\r
+ wr_ppu_status,\r
+ wr_ppu_scroll_x,\r
+ wr_ppu_scroll_y,\r
+\r
+ --vram i/f\r
+ wr_v_ce_n,\r
+ wr_v_rd_n,\r
+ wr_v_wr_n,\r
+ wr_v_addr,\r
+ wr_v_data,\r
+\r
+ --plt i/f\r
+ wr_plt_ce_n,\r
+ wr_plt_rd_n,\r
+ wr_plt_wr_n,\r
+ wr_plt_addr,\r
+ wr_plt_data,\r
+\r
+ --sprite i/f\r
+ wr_spr_ce_n,\r
+ wr_spr_rd_n,\r
+ wr_spr_wr_n,\r
+ wr_spr_addr,\r
+ wr_spr_data,\r
+\r
+ --vga output\r
+ po_h_sync_n,\r
+ po_v_sync_n,\r
+ po_r,\r
+ po_g,\r
+ po_b\r
);\r
\r
wr_rdy <= '1';\r
wr_irq_n <= '1';\r
wr_nmi_n <= '1';\r
\r
- po_h_sync_n <= '0';\r
- po_v_sync_n <= '0';\r
- po_r <= (others => '0');\r
- po_g <= (others => '0');\r
- po_b <= (others => '0');\r
+ po_dbg_cnt <= reg_dbg_cnt;\r
+ deb_cnt_p : process (pi_rst_n, pi_base_clk)\r
+use ieee.std_logic_unsigned.all;\r
+ variable cnt : integer;\r
+ begin\r
+ if (pi_rst_n = '0') then\r
+ reg_dbg_cnt <= (others => '0');\r
+ cnt := 0;\r
+ else\r
+ if (rising_edge(pi_base_clk)) then\r
+ if (cnt = 0) then\r
+ --debug count is half cycle because too fast to capture in st ii.\r
+ reg_dbg_cnt <= reg_dbg_cnt + 1;\r
+ cnt := 1;\r
+ else\r
+ cnt := 0;\r
+ end if;\r
+ end if;\r
+ end if;\r
+ end process;\r
end rtl;
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