rtl sim started...

[motonesfpga/motonesfpga.git] / de0_cv_nes / dummy-mos6502.vhd

diff --git a/de0_cv_nes/dummy-mos6502.vhd b/de0_cv_nes/dummy-mos6502.vhd
index 5435b49..19ab7de 100644 (file)
--- a/de0_cv_nes/dummy-mos6502.vhd
+++ b/de0_cv_nes/dummy-mos6502.vhd
@@ -4,6 +4,7 @@ use ieee.std_logic_1164.all;
 entity mos6502 is \r
     port (  \r
             pi_base_clk        : in std_logic;\r
+            pi_cpu_en       : in std_logic_vector (7 downto 0);\r
             pi_rdy         : in std_logic;\r
             pi_rst_n       : in std_logic;\r
             pi_irq_n       : in std_logic;\r
@@ -79,7 +80,7 @@ end;
             ref_cnt := 0;\r
 \r
         elsif (rising_edge(pi_base_clk)) then\r
-\r
+            if (pi_cpu_en(0) = '1') then\r
             if (pi_rdy = '1') then\r
                 if (init_done = '0') then\r
                     if (global_step_cnt = 0) then\r
@@ -516,6 +517,7 @@ end;
                 po_addr <= (others => 'Z');\r
                 pio_d_io <= (others => 'Z');\r
             end if;--if (rdy = '1') then\r
+            end if;--if (pi_cpu_en(0) = '1') then\r
         end if; --if (rst_n = '0') then\r
     end process;\r
 \r