debug update.

[motonesfpga/motonesfpga.git] / de0_cv_nes / mos6502.vhd

diff --git a/de0_cv_nes/mos6502.vhd b/de0_cv_nes/mos6502.vhd
index 6498320..a2e7641 100644 (file)
--- a/de0_cv_nes/mos6502.vhd
+++ b/de0_cv_nes/mos6502.vhd
@@ -245,18 +245,17 @@ signal reg_exc_cnt          : std_logic_vector (63 downto 0);
 --constant INIT_STATUS    : std_logic_vector (7 downto 0) := "00100000";\r
 --constant INIT_PCL       : std_logic_vector (7 downto 0) := "00000000";\r
 --constant INIT_PCH       : std_logic_vector (7 downto 0) := "00000000";\r
---constant INIT_EXC_CNT   : std_logic_vector (63 downto 0) := conv_std_logic_vector(16#0#, 64);\r
 \r
-constant INIT_ACC       : std_logic_vector (7 downto 0) := conv_std_logic_vector(16#91#, 8);\r
+constant INIT_ACC       : std_logic_vector (7 downto 0) := conv_std_logic_vector(16#95#, 8);\r
 constant INIT_X         : std_logic_vector (7 downto 0) := conv_std_logic_vector(16#0d#, 8);\r
 constant INIT_Y         : std_logic_vector (7 downto 0) := conv_std_logic_vector(16#1d#, 8);\r
 constant INIT_SP        : std_logic_vector (7 downto 0) := conv_std_logic_vector(16#fc#, 8);\r
 constant INIT_STATUS    : std_logic_vector (7 downto 0) := conv_std_logic_vector(16#a5#, 8);\r
 constant INIT_PCL       : std_logic_vector (7 downto 0) := conv_std_logic_vector(16#82#, 8);\r
 constant INIT_PCH       : std_logic_vector (7 downto 0) := conv_std_logic_vector(16#80#, 8);\r
-constant INIT_EXC_CNT   : std_logic_vector (63 downto 0) := conv_std_logic_vector(16#02b1#, 16) & conv_std_logic_vector(0, 48);\r
+constant INIT_EXC_CNT   : std_logic_vector (63 downto 0) := conv_std_logic_vector(16#02bd#, 16) & conv_std_logic_vector(0, 48);\r
 \r
-constant DEBUG_SW       : integer := 1;\r
+constant DEBUG_SW       : integer := 0;\r
 \r
 begin\r
     --state transition process...\r
@@ -2422,7 +2421,12 @@ end;
     exc_cnt_p : process (pi_rst_n, pi_base_clk)\r
     begin\r
         if (pi_rst_n = '0') then\r
-            reg_exc_cnt <= INIT_EXC_CNT;\r
+            if (DEBUG_SW = 0) then\r
+                reg_exc_cnt <= (others => '0');\r
+            else\r
+                --for test....\r
+                reg_exc_cnt <= INIT_EXC_CNT;\r
+            end if;\r
         else\r
             if (rising_edge(pi_base_clk)) then\r
                 if (reg_main_state = ST_CM_T0 and reg_sub_state = ST_SUB73) then\r