po_oe_n : out std_logic;\r
po_we_n : out std_logic;\r
po_addr : out std_logic_vector ( 15 downto 0);\r
- pio_d_io : inout std_logic_vector ( 7 downto 0)\r
+ pio_d_io : inout std_logic_vector ( 7 downto 0);\r
+ po_exc_cnt : out std_logic_vector (63 downto 0)\r
);\r
end mos6502;\r
\r
--48 49 4a 4b 4c 4d 4e 4f\r
ST_A51_T1, ST_A21_T1, ST_A1_T1, ST_INV, ST_A561_T1, ST_A23_T1, ST_A42_T1, ST_INV,\r
--50 51 52 53 54 55 56 57\r
- ST_A58_T1, ST_A27_T1, ST_INV, ST_INV, ST_A26_T1, ST_INV, ST_A43_T1, ST_INV,\r
+ ST_A58_T1, ST_A27_T1, ST_INV, ST_INV, ST_A26_T1, ST_A26_T1, ST_A43_T1, ST_INV,\r
--58 59 5a 5b 5c 5d 5e 5f\r
ST_A1_T1, ST_A25_T1, ST_INV, ST_INV, ST_INV, ST_A25_T1, ST_A44_T1, ST_INV,\r
--60 61 62 63 64 65 66 67\r
--68 69 6a 6b 6c 6d 6e 6f\r
ST_A52_T1, ST_A21_T1, ST_A1_T1, ST_INV, ST_A562_T1, ST_A23_T1, ST_A42_T1, ST_INV,\r
--70 71 72 73 74 75 76 77\r
- ST_A58_T1, ST_A27_T1, ST_INV, ST_INV, ST_A26_T1, ST_INV, ST_A43_T1, ST_INV,\r
+ ST_A58_T1, ST_A27_T1, ST_INV, ST_INV, ST_A26_T1, ST_A26_T1, ST_A43_T1, ST_INV,\r
--78 79 7a 7b 7c 7d 7e 7f\r
ST_A1_T1, ST_A25_T1, ST_INV, ST_INV, ST_INV, ST_A25_T1, ST_A44_T1, ST_INV,\r
--80 81 82 83 84 85 86 87\r
--a8 a9 aa ab ac ad ae af\r
ST_A1_T1, ST_A21_T1, ST_A1_T1, ST_INV, ST_A23_T1, ST_A23_T1, ST_A23_T1, ST_INV,\r
--b0 b1 b2 b3 b4 b5 b6 b7\r
- ST_A58_T1, ST_A27_T1, ST_INV, ST_A26_T1, ST_A26_T1, ST_A26_T1, ST_INV, ST_INV,\r
+ ST_A58_T1, ST_A27_T1, ST_INV, ST_A26_T1, ST_A26_T1, ST_A26_T1, ST_A26_T1, ST_INV,\r
--b8 b9 ba bb bc bd be bf\r
ST_A1_T1, ST_A25_T1, ST_A1_T1, ST_INV, ST_A25_T1, ST_A25_T1, ST_A25_T1, ST_INV,\r
--c0 c1 c2 c3 c4 c5 c6 c7\r
--c8 c9 ca cb cc cd ce cf\r
ST_A1_T1, ST_A21_T1, ST_A1_T1, ST_INV, ST_A23_T1, ST_A23_T1, ST_A42_T1, ST_INV,\r
--d0 d1 d2 d3 d4 d5 d6 d7\r
- ST_A58_T1, ST_A27_T1, ST_INV, ST_INV, ST_A26_T1, ST_INV, ST_A43_T1, ST_INV,\r
+ ST_A58_T1, ST_A27_T1, ST_INV, ST_INV, ST_A26_T1, ST_A26_T1, ST_A43_T1, ST_INV,\r
--d8 d9 da db dc dd de df\r
ST_A1_T1, ST_A25_T1, ST_INV, ST_INV, ST_INV, ST_A25_T1, ST_A44_T1, ST_INV,\r
--e0 e1 e2 e3 e4 e5 e6 e7\r
signal reg_nmi_handled : integer range 0 to 1;\r
signal reg_dma_set : integer range 0 to 1;\r
\r
+--debug purpose...\r
+signal reg_exc_cnt : std_logic_vector (63 downto 0);\r
+\r
+--constant INIT_ACC : std_logic_vector (7 downto 0) := "00000000";\r
+--constant INIT_X : std_logic_vector (7 downto 0) := "00000000";\r
+--constant INIT_Y : std_logic_vector (7 downto 0) := "00000000";\r
+--constant INIT_SP : std_logic_vector (7 downto 0) := "00000000";\r
+--constant INIT_STATUS : std_logic_vector (7 downto 0) := "00100000";\r
+--constant INIT_PCL : std_logic_vector (7 downto 0) := "00000000";\r
+--constant INIT_PCH : std_logic_vector (7 downto 0) := "00000000";\r
+\r
+constant INIT_ACC : std_logic_vector (7 downto 0) := conv_std_logic_vector(16#95#, 8);\r
+constant INIT_X : std_logic_vector (7 downto 0) := conv_std_logic_vector(16#0d#, 8);\r
+constant INIT_Y : std_logic_vector (7 downto 0) := conv_std_logic_vector(16#1d#, 8);\r
+constant INIT_SP : std_logic_vector (7 downto 0) := conv_std_logic_vector(16#fc#, 8);\r
+constant INIT_STATUS : std_logic_vector (7 downto 0) := conv_std_logic_vector(16#a5#, 8);\r
+constant INIT_PCL : std_logic_vector (7 downto 0) := conv_std_logic_vector(16#82#, 8);\r
+constant INIT_PCH : std_logic_vector (7 downto 0) := conv_std_logic_vector(16#80#, 8);\r
+constant INIT_EXC_CNT : std_logic_vector (63 downto 0) := conv_std_logic_vector(16#02bd#, 16) & conv_std_logic_vector(0, 48);\r
+\r
+constant DEBUG_SW : integer := 0;\r
\r
begin\r
--state transition process...\r
set_stat_p : process (pi_rst_n, pi_base_clk)\r
begin\r
if (pi_rst_n = '0') then\r
- reg_main_state <= ST_RS_T0;\r
+ if (DEBUG_SW = 0) then\r
+ reg_main_state <= ST_RS_T0;\r
+ else\r
+ --for test....\r
+ reg_main_state <= ST_CM_T0;\r
+ end if;\r
reg_sub_state <= ST_SUB00;\r
elsif (rising_edge(pi_base_clk)) then\r
reg_main_state <= reg_main_next_state;\r
-----idle...\r
when ST_IDLE =>\r
if (pi_rst_n = '0') then\r
- reg_main_next_state <= ST_RS_T0;\r
+ if (DEBUG_SW = 0) then\r
+ reg_main_next_state <= ST_RS_T0;\r
+ else\r
+ --for test....\r
+ reg_main_next_state <= ST_CM_T0;\r
+ end if;\r
elsif (reg_sub_state = ST_SUB73 and reg_dma_set = 1 and pi_rdy = '1') then\r
--ST_CM_T0 is canceled when dma initiated.\r
--redo ST_CM_T0.\r
\r
begin\r
if (pi_rst_n = '0') then\r
- reg_pc_l <= (others => '0');\r
- reg_pc_h <= (others => '0');\r
+ reg_pc_l <= INIT_PCL;\r
+ reg_pc_h <= INIT_PCH;\r
reg_inst <= (others => '0');\r
reg_addr <= (others => 'Z');\r
reg_d_out <= (others => 'Z');\r
if (reg_sub_state = ST_SUB00) then\r
reg_addr <= reg_pc_h & reg_pc_l;\r
elsif (reg_sub_state = ST_SUB70) then\r
- reg_pc_l <= reg_pc_l + 1;\r
+ pc_inc;\r
end if;\r
\r
--conditional branch.\r
sp_p : process (pi_rst_n, pi_base_clk)\r
begin\r
if (pi_rst_n = '0') then\r
- reg_sp <= (others => '0');\r
+ reg_sp <= INIT_SP;\r
elsif (rising_edge(pi_base_clk)) then\r
if (reg_main_state = ST_A1_T1) then\r
--txs inst.\r
begin\r
--Most instructions that explicitly reference memory locations have bit patterns of the form aaabbbcc.\r
if (pi_rst_n = '0') then\r
- reg_acc <= (others => '0');\r
- reg_x <= (others => '0');\r
- reg_y <= (others => '0');\r
- reg_status <= "00100000";\r
+ reg_acc <= INIT_ACC;\r
+ reg_x <= INIT_X;\r
+ reg_y <= INIT_Y;\r
+ reg_status <= INIT_STATUS;\r
reg_tmp_carry <= '0';\r
reg_tmp_ovf <= '0';\r
reg_tmp_condition <= '0';\r
calc_res := ("0" & reg_acc) - ("0" & reg_d_in) - not reg_status(FL_C);\r
\r
--c Set if unsigned borrow not required; cleared if unsigned borrow.\r
- reg_tmp_carry <= not calc_res(7);\r
+ reg_tmp_carry <= not calc_res(8);\r
--v Set if signed borrow required; cleared if no signed borrow.\r
if ((reg_acc(7) /= reg_d_in(7)) and (reg_acc(7) /= calc_res(7))) then\r
reg_tmp_ovf <= '1';\r
end if;--if (pi_rst_n = '0') then\r
end process;\r
\r
+ --debug cnt...\r
+ po_exc_cnt <= reg_exc_cnt;\r
+ exc_cnt_p : process (pi_rst_n, pi_base_clk)\r
+ begin\r
+ if (pi_rst_n = '0') then\r
+ if (DEBUG_SW = 0) then\r
+ reg_exc_cnt <= (others => '0');\r
+ else\r
+ --for test....\r
+ reg_exc_cnt <= INIT_EXC_CNT;\r
+ end if;\r
+ else\r
+ if (rising_edge(pi_base_clk)) then\r
+ if (reg_main_state = ST_CM_T0 and reg_sub_state = ST_SUB73) then\r
+ reg_exc_cnt <= reg_exc_cnt + 1;\r
+ elsif (reg_main_state = ST_NM_T7 and reg_sub_state = ST_SUB73) then\r
+ --reg_exc_cnt upper 16 bit is nmi count.\r
+ --lower 48 bit is cpu exec count from nmi initiated.\r
+ reg_exc_cnt(47 downto 0) <= (others => '0');\r
+ reg_exc_cnt(63 downto 48) <= reg_exc_cnt(63 downto 48) + 1;\r
+ end if;\r
+ end if;\r
+ end if;\r
+ end process;\r
end rtl;\r
\r
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