entity decoder is
generic (dsize : integer := 8);
port (
--- signal dbg_ea_carry : out std_logic;
-
-
+ --input lines.
set_clk : in std_logic;
trig_clk : in std_logic;
res_n : in std_logic;
instruction : in std_logic_vector (dsize - 1 downto 0);
exec_cycle : in std_logic_vector (5 downto 0);
next_cycle : out std_logic_vector (5 downto 0);
+ ea_carry : in std_logic;
status_reg : inout std_logic_vector (dsize - 1 downto 0);
+
+ --general control.
inst_we_n : out std_logic;
ad_oe_n : out std_logic;
dbuf_int_oe_n : out std_logic;
- dl_al_we_n : out std_logic;
- dl_ah_we_n : out std_logic;
- dl_al_oe_n : out std_logic;
- dl_ah_oe_n : out std_logic;
- dl_dh_oe_n : out std_logic;
- pcl_inc_n : out std_logic;
- pch_inc_n : out std_logic;
+ r_nw : out std_logic;
+
+ ----control line for dual port registers.
+ idl_l_cmd : out std_logic_vector(3 downto 0);
+ idl_h_cmd : out std_logic_vector(3 downto 0);
pcl_cmd : out std_logic_vector(3 downto 0);
pch_cmd : out std_logic_vector(3 downto 0);
sp_cmd : out std_logic_vector(3 downto 0);
+ x_cmd : out std_logic_vector(3 downto 0);
+ y_cmd : out std_logic_vector(3 downto 0);
+ acc_cmd : out std_logic_vector(3 downto 0);
+
+ --addr calc control
+ pcl_inc_n : out std_logic;
sp_oe_n : out std_logic;
sp_push_n : out std_logic;
sp_pop_n : out std_logic;
- acc_cmd : out std_logic_vector(3 downto 0);
- x_cmd : out std_logic_vector(3 downto 0);
- y_cmd : out std_logic_vector(3 downto 0);
abs_xy_n : out std_logic;
- ea_carry : in std_logic;
pg_next_n : out std_logic;
zp_n : out std_logic;
zp_xy_n : out std_logic;
indir_n : out std_logic;
indir_x_n : out std_logic;
indir_y_n : out std_logic;
- arith_en_n : out std_logic;
+ addr_cycle : out std_logic_vector(2 downto 0);
+
+ ---status register
stat_dec_oe_n : out std_logic;
stat_bus_oe_n : out std_logic;
stat_set_flg_n : out std_logic;
stat_bus_all_n : out std_logic;
stat_bus_nz_n : out std_logic;
stat_alu_we_n : out std_logic;
+
+ --ALU control
+ arith_en_n : out std_logic;
+ alu_cycle : out std_logic_vector(1 downto 0);
+
+ --reset vectors.
r_vec_oe_n : out std_logic;
n_vec_oe_n : out std_logic;
- i_vec_oe_n : out std_logic;
- r_nw : out std_logic
+ i_vec_oe_n : out std_logic
+
;---for parameter check purpose!!!
check_bit : out std_logic_vector(1 to 5)
);
constant T5 : std_logic_vector (5 downto 0) := "000101";
constant T6 : std_logic_vector (5 downto 0) := "000110";
---01xxx : reset cycle : R0 > R1 > R2 > R3 > R4 > R5 > T0
+--reset cycle:
+--R0/T0: hold pc
+--R1: hold pc
+--R2: push pch
+--R3: push pcl
+--R4: push p
+--R5: fetch vector low
+--R6: fetch vector high
+--T0: first opcode
+
+--01xxx : reset cycle : R0 > R1 > R2 > R3 > R4 > R5 > R6 > T0
constant R0 : std_logic_vector (5 downto 0) := "001000";
constant R1 : std_logic_vector (5 downto 0) := "001001";
constant R2 : std_logic_vector (5 downto 0) := "001010";
constant R3 : std_logic_vector (5 downto 0) := "001011";
constant R4 : std_logic_vector (5 downto 0) := "001100";
constant R5 : std_logic_vector (5 downto 0) := "001101";
+constant R6 : std_logic_vector (5 downto 0) := "001110";
---10xxx : nmi cycle : T0 > N1 > N2 > N3 > N4 > N5 > T0
+--10xxx : nmi cycle : T0 > N1 > N2 > N3 > N4 > N5 > N6 > T0
constant N1 : std_logic_vector (5 downto 0) := "010001";
constant N2 : std_logic_vector (5 downto 0) := "010010";
constant N3 : std_logic_vector (5 downto 0) := "010011";
constant N4 : std_logic_vector (5 downto 0) := "010100";
constant N5 : std_logic_vector (5 downto 0) := "010101";
+constant N6 : std_logic_vector (5 downto 0) := "010110";
---11xxx : irq cycle : T0 > I1 > I2 > I3 > I4 > I5 > T0
+--11xxx : irq cycle : T0 > I1 > I2 > I3 > I4 > I5 > I6 > T0
constant I1 : std_logic_vector (5 downto 0) := "011001";
constant I2 : std_logic_vector (5 downto 0) := "011010";
constant I3 : std_logic_vector (5 downto 0) := "011011";
constant I4 : std_logic_vector (5 downto 0) := "011100";
constant I5 : std_logic_vector (5 downto 0) := "011101";
+constant I6 : std_logic_vector (5 downto 0) := "011110";
constant ERROR_CYCLE : std_logic_vector (5 downto 0) := "111111";
constant st_Z : integer := 1;
constant st_C : integer := 0;
----for pch_inc_n.
-signal pch_inc_input : std_logic;
+--Address calcuration (indirect addressing) has several stages
+constant ADDR_Z : std_logic_vector (2 downto 0) := "000";
+constant ADDR_T2 : std_logic_vector (2 downto 0) := "001";
+constant ADDR_T3 : std_logic_vector (2 downto 0) := "010";
+constant ADDR_T4 : std_logic_vector (2 downto 0) := "011";
+constant ADDR_T5 : std_logic_vector (2 downto 0) := "100";
+
+--ALU cycle (memory to memory operation) has several stages
+constant MEM_Z : std_logic_vector (1 downto 0) := "00";
+constant MEM_T1 : std_logic_vector (1 downto 0) := "01";
+constant MEM_T2 : std_logic_vector (1 downto 0) := "10";
+constant MEM_T3 : std_logic_vector (1 downto 0) := "11";
---for nmi handling
signal nmi_handled_n : std_logic;
--- page boundary handling
-signal wk_next_cycle : std_logic_vector (5 downto 0);
-signal wk_acc_cmd : std_logic_vector(3 downto 0);
-signal wk_x_cmd : std_logic_vector(3 downto 0);
-signal wk_y_cmd : std_logic_vector(3 downto 0);
-signal wk_stat_alu_we_n : std_logic;
signal ea_carry_reg : std_logic;
begin
- ---pc page next is connected to top bit of exec_cycle
- pch_inc_input <= not exec_cycle(5);
- pch_inc_reg : d_flip_flop_bit
- port map(set_clk, '1', '1', '0', pch_inc_input, pch_inc_n);
-
ea_carry_inst: d_flip_flop_bit
port map(trig_clk, '1', '1', '0', ea_carry, ea_carry_reg);
- --acc,x,y next cycle is changed when it goes page across.
- --The conditional branch instructions all have the form xxy10000
- next_cycle <= wk_next_cycle;
- acc_cmd <= wk_acc_cmd(3) & '1' & wk_acc_cmd(1) & '1'
- when ea_carry = '1' and
- wk_next_cycle = T0 and instruction(4 downto 0) = "10000" else
- wk_acc_cmd;
-
- x_cmd <= wk_x_cmd(3) & '1' & wk_x_cmd(1 downto 0)
- when ea_carry = '1' and
- wk_next_cycle = T0 and instruction(4 downto 0) = "10000" else
- wk_x_cmd;
- y_cmd <= wk_y_cmd(3) & '1' & wk_y_cmd(1 downto 0)
- when ea_carry = '1' and
- wk_next_cycle = T0 and instruction(4 downto 0) = "10000" else
- wk_y_cmd;
- stat_alu_we_n <= '1' when ea_carry = '1' and
- wk_next_cycle = T0 and instruction(4 downto 0) = "10000" else
- wk_stat_alu_we_n;
-
main_p : process (set_clk, res_n, nmi_n)
-------------------------------------------------------------
back_oe(pcl_cmd, '0');
back_oe(pch_cmd, '0');
back_we(pcl_cmd, '0');
- back_we(pch_cmd, '1');
+ back_we(pch_cmd, '0');
+ if exec_cycle = T1 then
+ front_we(idl_l_cmd, '0');
+ elsif exec_cycle = T2 then
+ front_we(idl_l_cmd, '1');
+ front_we(idl_h_cmd, '0');
+ end if;
end procedure;
procedure fetch_stop is
back_oe(pcl_cmd, '1');
back_oe(pch_cmd, '1');
back_we(pcl_cmd, '1');
+ back_we(pch_cmd, '1');
+ front_we(idl_l_cmd, '1');
+ front_we(idl_h_cmd, '1');
end procedure;
procedure read_status is
stat_dec_oe_n <= '0';
end procedure;
+procedure init_all_pins is
+begin
+ --initialize port...
+ inst_we_n <= '1';
+ ad_oe_n <= '1';
+ dbuf_int_oe_n <= '1';
+ r_nw <= '1';
+
+ idl_l_cmd <= "1111";
+ idl_h_cmd <= "1111";
+ pcl_cmd <= "1111";
+ pch_cmd <= "1111";
+ sp_cmd <= "1111";
+ x_cmd <= "1111";
+ y_cmd <= "1111";
+ acc_cmd <= "1111";
+
+ pcl_inc_n <= '1';
+ sp_oe_n <= '1';
+ sp_push_n <= '1';
+ sp_pop_n <= '1';
+ abs_xy_n <= '1';
+ pg_next_n <= '1';
+ zp_n <= '1';
+ zp_xy_n <= '1';
+ rel_calc_n <= '1';
+ indir_n <= '1';
+ indir_x_n <= '1';
+ indir_y_n <= '1';
+ addr_cycle <= ADDR_Z;
+
+ read_status;
+ stat_bus_oe_n <= '1';
+ stat_set_flg_n <= '1';
+ stat_flg <= '1';
+ stat_bus_all_n <= '1';
+ stat_bus_nz_n <= '1';
+ stat_alu_we_n <= '1';
+
+ arith_en_n <= '1';
+ addr_cycle <= ADDR_Z;
+
+ r_vec_oe_n <= '1';
+ n_vec_oe_n <= '1';
+ i_vec_oe_n <= '1';
+
+ nmi_handled_n <= '1';
+
+end procedure;
+
procedure disable_pins is
begin
--following pins are not set in this function.
-- inst_we_n : out std_logic;
-- ad_oe_n : out std_logic;
--- dl_al_oe_n : out std_logic;
-- pcl_inc_n : out std_logic;
--- pcl_cmd : out std_logic_vector(3 downto 0);
--- pch_cmd : out std_logic_vector(3 downto 0);
-- r_nw : out std_logic
--disable the last opration pins.
dbuf_int_oe_n <= '1';
- dl_al_we_n <= '1';
- dl_ah_we_n <= '1';
- dl_ah_oe_n <= '1';
- dl_dh_oe_n <= '1';
+
+ idl_l_cmd <= "1111";
+ idl_h_cmd <= "1111";
+ pcl_cmd <= "1111";
+ pch_cmd <= "1111";
sp_cmd <= "1111";
+ x_cmd <= "1111";
+ y_cmd <= "1111";
+ acc_cmd <= "1111";
+
sp_oe_n <= '1';
sp_push_n <= '1';
sp_pop_n <= '1';
- wk_acc_cmd <= "1111";
- wk_x_cmd <= "1111";
- wk_y_cmd <= "1111";
-
abs_xy_n <= '1';
pg_next_n <= '1';
zp_n <= '1';
indir_n <= '1';
indir_x_n <= '1';
indir_y_n <= '1';
- arith_en_n <= '1';
+ addr_cycle <= ADDR_Z;
read_status;
stat_bus_oe_n <= '1';
stat_flg <= '1';
stat_bus_all_n <= '1';
stat_bus_nz_n <= '1';
- wk_stat_alu_we_n <= '1';
+ stat_alu_we_n <= '1';
+
+ arith_en_n <= '1';
+ alu_cycle <= MEM_Z;
r_vec_oe_n <= '1';
n_vec_oe_n <= '1';
end procedure;
-procedure fetch_inst (inc_pcl : in std_logic) is
+procedure fetch_inst (pm_pcl_inc_n : in std_logic) is
begin
if instruction = conv_std_logic_vector(16#4c#, dsize) then
--if prior cycle is jump instruction,
--fetch opcode from where the latch is pointing to.
--latch > al.
- dl_al_oe_n <= '0';
+ back_oe(idl_l_cmd, '0');
pcl_cmd <= "1110";
else
--fetch opcode and pcl increment.
pcl_cmd <= "1100";
- dl_al_oe_n <= '1';
end if;
+ idl_h_cmd <= "1111";
ad_oe_n <= '0';
- pch_cmd <= "1101";
+ pch_cmd <= "1100";
inst_we_n <= '0';
- pcl_inc_n <= inc_pcl;
+ pcl_inc_n <= pm_pcl_inc_n;
r_nw <= '1';
d_print(string'("fetch 1"));
if (nmi_n = '0' and nmi_handled_n = '1') then
--start nmi handling...
fetch_inst('1');
- wk_next_cycle <= N1;
+ next_cycle <= N1;
else
fetch_inst('0');
- wk_next_cycle <= T1;
+ next_cycle <= T1;
end if;
end procedure;
procedure single_inst is
begin
fetch_stop;
- wk_next_cycle <= T0;
+ next_cycle <= T0;
end procedure;
procedure fetch_imm is
--send data from data bus buffer.
--receiver is instruction dependent.
dbuf_int_oe_n <= '0';
- wk_next_cycle <= T0;
+ next_cycle <= T0;
end procedure;
procedure set_nz_from_bus is
procedure set_zc_from_alu is
begin
--status register n/z bit update.
- wk_stat_alu_we_n <= '0';
+ stat_alu_we_n <= '0';
stat_dec_oe_n <= '1';
status_reg <= "00000011";
end procedure;
procedure set_nz_from_alu is
begin
--status register n/z/c bit update.
- wk_stat_alu_we_n <= '0';
+ stat_alu_we_n <= '0';
stat_dec_oe_n <= '1';
status_reg <= "10000010";
end procedure;
procedure set_nzc_from_alu is
begin
--status register n/z/c bit update.
- wk_stat_alu_we_n <= '0';
+ stat_alu_we_n <= '0';
stat_dec_oe_n <= '1';
status_reg <= "10000011";
end procedure;
procedure set_nvz_from_alu is
begin
--status register n/z/v bit update.
- wk_stat_alu_we_n <= '0';
+ stat_alu_we_n <= '0';
stat_dec_oe_n <= '1';
status_reg <= "11000010";
end procedure;
procedure set_nvzc_from_alu is
begin
- wk_stat_alu_we_n <= '0';
+ stat_alu_we_n <= '0';
stat_dec_oe_n <= '1';
status_reg <= "11000011";
end procedure;
fetch_next;
--latch abs low data.
dbuf_int_oe_n <= '0';
- dl_al_we_n <= '0';
- wk_next_cycle <= T2;
+ next_cycle <= T2;
end procedure;
procedure abs_fetch_high is
begin
d_print("abs (xy) 3");
- dl_al_we_n <= '1';
--latch abs hi data.
fetch_next;
dbuf_int_oe_n <= '0';
- dl_ah_we_n <= '0';
- wk_next_cycle <= T3;
+ next_cycle <= T3;
end procedure;
procedure abs_latch_out is
begin
--d_print("abs 4");
- dl_ah_we_n <= '1';
fetch_stop;
--latch > al/ah.
- dl_al_oe_n <= '0';
- dl_ah_oe_n <= '0';
+ back_oe(idl_l_cmd, '0');
+ back_oe(idl_h_cmd, '0');
end procedure;
procedure ea_x_out is
begin
-----calucurate and output effective addr
- back_oe(wk_x_cmd, '0');
+ back_oe(x_cmd, '0');
abs_xy_n <= '0';
end procedure;
procedure ea_y_out is
begin
- back_oe(wk_y_cmd, '0');
+ back_oe(y_cmd, '0');
abs_xy_n <= '0';
end procedure;
elsif exec_cycle = T2 then
fetch_stop;
dbuf_int_oe_n <= '0';
- dl_al_we_n <= '1';
--calc zp.
- dl_al_oe_n <= '0';
+ back_oe(idl_l_cmd, '0');
zp_n <= '0';
- wk_next_cycle <= T0;
+ next_cycle <= T0;
end if;
end procedure;
elsif exec_cycle = T3 then
abs_latch_out;
dbuf_int_oe_n <= '0';
- wk_next_cycle <= T0;
+ next_cycle <= T0;
end if;
end procedure;
-procedure a2_page_next is
-begin
- --close open gate if page boundary crossed.
- back_we(wk_acc_cmd, '1');
- front_we(wk_acc_cmd, '1');
- front_we(wk_x_cmd, '1');
- front_we(wk_y_cmd, '1');
- wk_stat_alu_we_n <= '1';
-end procedure;
-
procedure a2_abs_xy (is_x : in boolean) is
begin
if exec_cycle = T1 then
end if;
dbuf_int_oe_n <= '0';
- wk_next_cycle <= T0;
+ next_cycle <= T0;
d_print("absx step 1");
elsif (exec_cycle = T0 and ea_carry_reg = '1') then
--case page boundary crossed.
d_print("absx 5 (page boudary crossed.)");
--next page.
pg_next_n <= '0';
- wk_next_cycle <= T0;
+ next_cycle <= T0;
end if;
end procedure;
fetch_stop;
--output BAL only
dbuf_int_oe_n <= '0';
- dl_al_we_n <= '1';
--calc zp.
- dl_al_oe_n <= '0';
+ back_oe(idl_l_cmd, '0');
zp_n <= '0';
- wk_next_cycle <= T3;
+ next_cycle <= T3;
elsif exec_cycle = T3 then
--t3 zp, xy
zp_xy_n <= '0';
if (is_x = true) then
- back_oe(wk_x_cmd, '0');
+ back_oe(x_cmd, '0');
else
- back_oe(wk_y_cmd, '0');
+ back_oe(y_cmd, '0');
end if;
- wk_next_cycle <= T0;
+ next_cycle <= T0;
end if;
end procedure;
if exec_cycle = T1 then
fetch_low;
--get IAL
- dl_al_we_n <= '0';
elsif exec_cycle = T2 then
fetch_stop;
- dl_al_we_n <= '1';
---address is 00:IAL
--output BAL @IAL
indir_y_n <= '0';
- dl_al_oe_n <= '0';
+ addr_cycle <= ADDR_T2;
+ back_oe(idl_l_cmd, '0');
dbuf_int_oe_n <= '0';
- wk_next_cycle <= T3;
+ next_cycle <= T3;
elsif exec_cycle = T3 then
indir_y_n <= '0';
- dl_al_oe_n <= '0';
+ addr_cycle <= ADDR_T3;
+ back_oe(idl_l_cmd, '0');
--output BAH @IAL+1
dbuf_int_oe_n <= '0';
- wk_next_cycle <= T4;
+ next_cycle <= T4;
elsif exec_cycle = T4 then
- dl_al_oe_n <= '1';
+ back_oe(idl_l_cmd, '1');
dbuf_int_oe_n <= '1';
--add index y.
pg_next_n <= '1';
- back_oe(wk_y_cmd, '0');
+ back_oe(y_cmd, '0');
indir_y_n <= '0';
+ addr_cycle <= ADDR_T4;
dbuf_int_oe_n <= '0';
- if (ea_carry = '1') then
- wk_next_cycle <= T5;
- else
- wk_next_cycle <= T0;
- end if;
- elsif (exec_cycle = T5) then
+ next_cycle <= T0;
+ elsif (exec_cycle = T0) then
--case page boundary crossed.
--redo inst.
d_print("(indir), y (page boudary crossed.)");
--next page.
+ indir_y_n <= '0';
pg_next_n <= '0';
- wk_next_cycle <= T0;
+ addr_cycle <= ADDR_T5;
+ next_cycle <= T0;
end if;
end procedure;
if exec_cycle = T1 then
fetch_low;
--get IAL
- dl_al_we_n <= '0';
elsif exec_cycle = T2 then
fetch_stop;
- dl_al_we_n <= '1';
---address is 00:IAL
--output BAL @IAL, but cycle #2 is discarded
indir_x_n <= '0';
- dl_al_oe_n <= '0';
- wk_next_cycle <= T3;
+ addr_cycle <= ADDR_T2;
+ back_oe(idl_l_cmd, '0');
+ next_cycle <= T3;
elsif exec_cycle = T3 then
indir_x_n <= '0';
- dl_al_oe_n <= '1';
+ addr_cycle <= ADDR_T3;
+ back_oe(idl_l_cmd, '1');
--output BAH @IAL+x
dbuf_int_oe_n <= '0';
- back_oe(wk_x_cmd, '0');
- wk_next_cycle <= T4;
+ back_oe(x_cmd, '0');
+ next_cycle <= T4;
elsif exec_cycle = T4 then
indir_x_n <= '0';
+ addr_cycle <= ADDR_T4;
--output BAH @IAL+x+1
dbuf_int_oe_n <= '0';
- back_oe(wk_x_cmd, '0');
+ back_oe(x_cmd, '0');
- wk_next_cycle <= T5;
+ next_cycle <= T5;
elsif (exec_cycle = T5) then
indir_x_n <= '0';
- wk_next_cycle <= T0;
+ addr_cycle <= ADDR_T5;
+ next_cycle <= T0;
end if;
end procedure;
elsif exec_cycle = T2 then
fetch_stop;
dbuf_int_oe_n <= '1';
- dl_al_we_n <= '1';
--calc zp.
- dl_al_oe_n <= '0';
+ back_oe(idl_l_cmd, '0');
zp_n <= '0';
r_nw <= '0';
- wk_next_cycle <= T0;
+ next_cycle <= T0;
end if;
end procedure;
elsif exec_cycle = T2 then
fetch_stop;
dbuf_int_oe_n <= '1';
- dl_al_we_n <= '1';
--calc zp.
- dl_al_oe_n <= '0';
+ back_oe(idl_l_cmd, '0');
zp_n <= '0';
- wk_next_cycle <= T3;
+ next_cycle <= T3;
elsif exec_cycle = T3 then
--calc zp + index.
- dl_al_oe_n <= '0';
+ back_oe(idl_l_cmd, '0');
zp_n <= '0';
zp_xy_n <= '0';
if (is_x = true) then
- back_oe(wk_x_cmd, '0');
+ back_oe(x_cmd, '0');
else
- back_oe(wk_y_cmd, '0');
+ back_oe(y_cmd, '0');
end if;
--write data
r_nw <= '0';
- wk_next_cycle <= T0;
+ next_cycle <= T0;
end if;
end procedure;
abs_latch_out;
dbuf_int_oe_n <= '1';
r_nw <= '0';
- wk_next_cycle <= T0;
+ next_cycle <= T0;
end if;
end procedure;
else
ea_y_out;
end if;
- wk_next_cycle <= T4;
+ next_cycle <= T4;
elsif exec_cycle = T4 then
if (ea_carry_reg = '1') then
pg_next_n <= '0';
ea_y_out;
end if;
r_nw <= '0';
- wk_next_cycle <= T0;
+ next_cycle <= T0;
end if;
end procedure;
if exec_cycle = T1 then
fetch_low;
--get IAL
- dl_al_we_n <= '0';
elsif exec_cycle = T2 then
fetch_stop;
- dl_al_we_n <= '1';
---address is 00:IAL
--output BAL @IAL
indir_y_n <= '0';
- dl_al_oe_n <= '0';
+ addr_cycle <= ADDR_T2;
+ back_oe(idl_l_cmd, '0');
dbuf_int_oe_n <= '0';
- wk_next_cycle <= T3;
+ next_cycle <= T3;
elsif exec_cycle = T3 then
indir_y_n <= '0';
- dl_al_oe_n <= '0';
+ addr_cycle <= ADDR_T3;
+ back_oe(idl_l_cmd, '0');
--output BAH @IAL+1
dbuf_int_oe_n <= '0';
- wk_next_cycle <= T4;
+ next_cycle <= T4;
elsif exec_cycle = T4 then
- dl_al_oe_n <= '1';
+ back_oe(idl_l_cmd, '1');
dbuf_int_oe_n <= '1';
--add index y.
pg_next_n <= '1';
- back_oe(wk_y_cmd, '0');
+ back_oe(y_cmd, '0');
indir_y_n <= '0';
- wk_next_cycle <= T5;
+ addr_cycle <= ADDR_T4;
+ next_cycle <= T5;
elsif exec_cycle = T5 then
--page handling.
- back_oe(wk_y_cmd, '1');
+ back_oe(y_cmd, '1');
indir_y_n <= '0';
+ addr_cycle <= ADDR_T5;
- --ea_carry reg is suspicious. timing is not garanteed...
if (ea_carry_reg = '1') then
pg_next_n <= '0';
else
pg_next_n <= '1';
end if;
r_nw <= '0';
- wk_next_cycle <= T0;
+ next_cycle <= T0;
end if;
end procedure;
if exec_cycle = T1 then
fetch_low;
--get IAL
- dl_al_we_n <= '0';
elsif exec_cycle = T2 then
fetch_stop;
- dl_al_we_n <= '1';
---address is 00:IAL
--output BAL @IAL, but cycle #2 is discarded
indir_x_n <= '0';
- dl_al_oe_n <= '0';
- wk_next_cycle <= T3;
+ addr_cycle <= ADDR_T2;
+ back_oe(idl_l_cmd, '0');
+ next_cycle <= T3;
elsif exec_cycle = T3 then
indir_x_n <= '0';
- dl_al_oe_n <= '1';
+ addr_cycle <= ADDR_T3;
+ back_oe(idl_l_cmd, '1');
--output BAH @IAL+x
dbuf_int_oe_n <= '0';
- back_oe(wk_x_cmd, '0');
- wk_next_cycle <= T4;
+ back_oe(x_cmd, '0');
+ next_cycle <= T4;
elsif exec_cycle = T4 then
indir_x_n <= '0';
+ addr_cycle <= ADDR_T4;
--output BAH @IAL+x+1
dbuf_int_oe_n <= '0';
- back_oe(wk_x_cmd, '0');
+ back_oe(x_cmd, '0');
- wk_next_cycle <= T5;
+ next_cycle <= T5;
elsif (exec_cycle = T5) then
indir_x_n <= '0';
+ addr_cycle <= ADDR_T5;
dbuf_int_oe_n <= '1';
r_nw <= '0';
- wk_next_cycle <= T0;
+ next_cycle <= T0;
end if;
end procedure;
fetch_low;
elsif exec_cycle = T2 then
fetch_stop;
- dl_al_we_n <= '1';
--t2 cycle read and,
- dl_al_oe_n <= '0';
+ back_oe(idl_l_cmd, '0');
zp_n <= '0';
--keep data in the alu reg.
arith_en_n <= '0';
+ alu_cycle <= MEM_T1;
dbuf_int_oe_n <= '0';
- wk_next_cycle <= T3;
+ next_cycle <= T3;
elsif exec_cycle = T3 then
--t3 fix alu internal register.
- dl_al_oe_n <= '0';
+ back_oe(idl_l_cmd, '0');
zp_n <= '0';
arith_en_n <= '0';
+ alu_cycle <= MEM_T2;
dbuf_int_oe_n <= '1';
- wk_next_cycle <= T4;
+ next_cycle <= T4;
elsif exec_cycle = T4 then
--t5 cycle writes modified value.
- dl_al_oe_n <= '0';
+ back_oe(idl_l_cmd, '0');
zp_n <= '0';
r_nw <= '0';
arith_en_n <= '0';
- wk_next_cycle <= T0;
+ alu_cycle <= MEM_T3;
+ next_cycle <= T0;
end if;
end procedure;
elsif exec_cycle = T2 then
fetch_stop;
dbuf_int_oe_n <= '1';
- dl_al_we_n <= '1';
--t2 cycle read bal only.
- dl_al_oe_n <= '0';
+ back_oe(idl_l_cmd, '0');
zp_n <= '0';
- wk_next_cycle <= T3;
+ next_cycle <= T3;
elsif exec_cycle = T3 then
--t3 cycle read bal + x
- dl_al_oe_n <= '0';
+ back_oe(idl_l_cmd, '0');
zp_n <= '0';
zp_xy_n <= '0';
- back_oe(wk_x_cmd, '0');
+ back_oe(x_cmd, '0');
--keep data in the alu reg.
arith_en_n <= '0';
+ alu_cycle <= MEM_T1;
dbuf_int_oe_n <= '0';
- wk_next_cycle <= T4;
+ next_cycle <= T4;
elsif exec_cycle = T4 then
- dl_al_oe_n <= '0';
+ back_oe(idl_l_cmd, '0');
zp_n <= '0';
zp_xy_n <= '0';
- back_oe(wk_x_cmd, '0');
+ back_oe(x_cmd, '0');
--fix alu internal register.
arith_en_n <= '0';
+ alu_cycle <= MEM_T2;
dbuf_int_oe_n <= '1';
- wk_next_cycle <= T5;
+ next_cycle <= T5;
elsif exec_cycle = T5 then
dbuf_int_oe_n <= '1';
--t5 cycle writes modified value.
- dl_al_oe_n <= '0';
+ back_oe(idl_l_cmd, '0');
zp_n <= '0';
zp_xy_n <= '0';
- back_oe(wk_x_cmd, '0');
+ back_oe(x_cmd, '0');
r_nw <= '0';
arith_en_n <= '0';
- wk_next_cycle <= T0;
+ alu_cycle <= MEM_T3;
+ next_cycle <= T0;
end if;
end procedure;
--keep data in the alu reg.
arith_en_n <= '0';
+ alu_cycle <= MEM_T1;
dbuf_int_oe_n <= '0';
- wk_next_cycle <= T4;
+ next_cycle <= T4;
elsif exec_cycle = T4 then
abs_latch_out;
--fix alu internal register.
arith_en_n <= '0';
+ alu_cycle <= MEM_T2;
dbuf_int_oe_n <= '1';
- wk_next_cycle <= T5;
+ next_cycle <= T5;
elsif exec_cycle = T5 then
dbuf_int_oe_n <= '1';
--t5 cycle writes modified value.
r_nw <= '0';
arith_en_n <= '0';
- wk_next_cycle <= T0;
+ alu_cycle <= MEM_T3;
+ next_cycle <= T0;
end if;
end procedure;
abs_latch_out;
ea_x_out;
dbuf_int_oe_n <= '0';
- wk_next_cycle <= T4;
+ next_cycle <= T4;
elsif exec_cycle = T4 then
abs_latch_out;
--keep data in the alu reg.
arith_en_n <= '0';
+ alu_cycle <= MEM_T1;
dbuf_int_oe_n <= '0';
- wk_next_cycle <= T5;
+ next_cycle <= T5;
elsif exec_cycle = T5 then
--fix alu internal register.
arith_en_n <= '0';
+ alu_cycle <= MEM_T2;
dbuf_int_oe_n <= '1';
- wk_next_cycle <= T6;
+ next_cycle <= T6;
elsif exec_cycle = T6 then
--t5 cycle writes modified value.
r_nw <= '0';
arith_en_n <= '0';
- wk_next_cycle <= T0;
+ alu_cycle <= MEM_T3;
+ next_cycle <= T0;
end if;
end procedure;
begin
if exec_cycle = T1 then
fetch_stop;
- wk_next_cycle <= T2;
+ next_cycle <= T2;
elsif exec_cycle = T2 then
back_oe(sp_cmd, '0');
back_we(sp_cmd, '0');
sp_push_n <= '0';
sp_oe_n <= '0';
r_nw <= '0';
- wk_next_cycle <= T0;
+ next_cycle <= T0;
end if;
end procedure;
begin
if exec_cycle = T1 then
fetch_stop;
- wk_next_cycle <= T2;
+ next_cycle <= T2;
elsif exec_cycle = T2 then
--stack decrement first.
back_we(sp_cmd, '0');
sp_pop_n <= '0';
sp_oe_n <= '0';
- wk_next_cycle <= T3;
+ next_cycle <= T3;
elsif exec_cycle = T3 then
sp_pop_n <= '1';
back_oe(sp_cmd, '0');
sp_oe_n <= '0';
dbuf_int_oe_n <= '0';
- wk_next_cycle <= T0;
+ next_cycle <= T0;
end if;
end procedure;
--latch rel value.
dbuf_int_oe_n <= '0';
- dl_ah_we_n <= '0';
- wk_next_cycle <= T2;
+ front_we(idl_h_cmd, '0');
+ next_cycle <= T2;
else
d_print("no branch");
- wk_next_cycle <= T0;
+ next_cycle <= T0;
end if;
elsif exec_cycle = T2 then
d_print("rel ea");
fetch_stop;
dbuf_int_oe_n <= '1';
- dl_ah_we_n <= '1';
+ front_we(idl_h_cmd, '1');
--calc relative addr.
rel_calc_n <= '0';
pg_next_n <= '1';
- dl_dh_oe_n <= '0';
+ front_oe(idl_h_cmd, '0');
back_oe(pcl_cmd, '0');
back_oe(pch_cmd, '0');
back_we(pcl_cmd, '0');
- wk_next_cycle <= T0;
+ next_cycle <= T0;
elsif (exec_cycle = T0 and ea_carry = '1') then
d_print("page crossed.");
--page crossed. adh calc.
back_oe(pcl_cmd, '0');
back_oe(pch_cmd, '0');
back_we(pch_cmd, '0');
- dl_dh_oe_n <= '0';
+ front_oe(idl_h_cmd, '0');
rel_calc_n <= '0';
pg_next_n <= '0';
- wk_next_cycle <= T0;
+ next_cycle <= T0;
end if;
end procedure;
stat_flg <= '1';
stat_bus_all_n <= '1';
stat_bus_nz_n <= '1';
- wk_stat_alu_we_n <= '1';
+ stat_alu_we_n <= '1';
--pc l/h is reset vector.
pcl_cmd <= "1110";
pch_cmd <= "1110";
- wk_next_cycle <= R0;
+ next_cycle <= R0;
elsif (rising_edge(set_clk)) then
d_print(string'("-"));
disable_pins;
inst_we_n <= '1';
ad_oe_n <= '1';
- dl_al_oe_n <= '1';
+ back_oe(idl_l_cmd, '1');
pcl_inc_n <= '1';
pcl_cmd <= "1111";
pch_cmd <= "1111";
r_nw <= 'Z';
+
elsif (exec_cycle = T0 and ea_carry = '0') then
--cycle #1
t0_cycle;
d_print("decode and execute inst: "
& conv_hex8(conv_integer(instruction)));
--disable pin for jmp instruction
- dl_al_oe_n <= '1';
+ back_oe(idl_l_cmd, '1');
back_we(pcl_cmd, '1');
front_we(pch_cmd, '1');
--asl acc mode.
d_print("asl");
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- front_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ front_we(acc_cmd, '0');
set_nzc_from_alu;
single_inst;
elsif instruction = conv_std_logic_vector(16#ca#, dsize) then
d_print("dex");
arith_en_n <= '0';
- back_oe(wk_x_cmd, '0');
- front_we(wk_x_cmd, '0');
+ back_oe(x_cmd, '0');
+ front_we(x_cmd, '0');
--set nz bit.
set_nz_from_bus;
single_inst;
elsif instruction = conv_std_logic_vector(16#88#, dsize) then
d_print("dey");
arith_en_n <= '0';
- back_oe(wk_y_cmd, '0');
- front_we(wk_y_cmd, '0');
+ back_oe(y_cmd, '0');
+ front_we(y_cmd, '0');
--set nz bit.
set_nz_from_bus;
single_inst;
elsif instruction = conv_std_logic_vector(16#e8#, dsize) then
d_print("inx");
arith_en_n <= '0';
- back_oe(wk_x_cmd, '0');
- front_we(wk_x_cmd, '0');
+ back_oe(x_cmd, '0');
+ front_we(x_cmd, '0');
--set nz bit.
set_nz_from_bus;
single_inst;
elsif instruction = conv_std_logic_vector(16#c8#, dsize) then
d_print("iny");
arith_en_n <= '0';
- back_oe(wk_y_cmd, '0');
- front_we(wk_y_cmd, '0');
+ back_oe(y_cmd, '0');
+ front_we(y_cmd, '0');
set_nz_from_bus;
single_inst;
--lsr acc mode
d_print("lsr");
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- front_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ front_we(acc_cmd, '0');
set_zc_from_alu;
single_inst;
--rol acc
d_print("rol");
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- front_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ front_we(acc_cmd, '0');
set_nzc_from_alu;
single_inst;
--ror acc
d_print("ror");
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- front_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ front_we(acc_cmd, '0');
set_nzc_from_alu;
single_inst;
d_print("tax");
set_nz_from_bus;
single_inst;
- front_oe(wk_acc_cmd, '0');
- front_we(wk_x_cmd, '0');
+ front_oe(acc_cmd, '0');
+ front_we(x_cmd, '0');
elsif instruction = conv_std_logic_vector(16#a8#, dsize) then
d_print("tay");
set_nz_from_bus;
single_inst;
- front_oe(wk_acc_cmd, '0');
- front_we(wk_y_cmd, '0');
+ front_oe(acc_cmd, '0');
+ front_we(y_cmd, '0');
elsif instruction = conv_std_logic_vector(16#ba#, dsize) then
d_print("tsx");
set_nz_from_bus;
single_inst;
front_oe(sp_cmd, '0');
- front_we(wk_x_cmd, '0');
+ front_we(x_cmd, '0');
elsif instruction = conv_std_logic_vector(16#8a#, dsize) then
d_print("txa");
set_nz_from_bus;
single_inst;
- front_oe(wk_x_cmd, '0');
- front_we(wk_acc_cmd, '0');
+ front_oe(x_cmd, '0');
+ front_we(acc_cmd, '0');
elsif instruction = conv_std_logic_vector(16#9a#, dsize) then
d_print("txs");
set_nz_from_bus;
single_inst;
- front_oe(wk_x_cmd, '0');
+ front_oe(x_cmd, '0');
front_we(sp_cmd, '0');
elsif instruction = conv_std_logic_vector(16#98#, dsize) then
d_print("tya");
set_nz_from_bus;
single_inst;
- front_oe(wk_y_cmd, '0');
- front_we(wk_acc_cmd, '0');
+ front_oe(y_cmd, '0');
+ front_we(acc_cmd, '0');
d_print("adc");
fetch_imm;
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- back_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ back_we(acc_cmd, '0');
set_nvzc_from_alu;
elsif instruction = conv_std_logic_vector(16#65#, dsize) then
a2_zp;
if exec_cycle = T2 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- back_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ back_we(acc_cmd, '0');
set_nvzc_from_alu;
end if;
a2_zp_xy(true);
if exec_cycle = T3 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- back_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ back_we(acc_cmd, '0');
set_nvzc_from_alu;
end if;
a2_abs;
if exec_cycle = T3 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- back_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ back_we(acc_cmd, '0');
set_nvzc_from_alu;
end if;
a2_abs_xy(true);
if exec_cycle = T3 or exec_cycle = T0 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- back_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ back_we(acc_cmd, '0');
set_nvzc_from_alu;
end if;
a2_abs_xy(false);
if exec_cycle = T3 or exec_cycle = T0 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- back_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ back_we(acc_cmd, '0');
set_nvzc_from_alu;
end if;
a2_indir_x;
if exec_cycle = T5 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- back_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ back_we(acc_cmd, '0');
set_nvzc_from_alu;
end if;
a2_indir_y;
if exec_cycle = T4 or exec_cycle = T0 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- back_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ back_we(acc_cmd, '0');
set_nvzc_from_alu;
end if;
d_print("and");
fetch_imm;
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- back_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ back_we(acc_cmd, '0');
set_nz_from_alu;
elsif instruction = conv_std_logic_vector(16#25#, dsize) then
a2_zp;
if exec_cycle = T2 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- back_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ back_we(acc_cmd, '0');
set_nz_from_alu;
end if;
a2_zp_xy(true);
if exec_cycle = T3 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- back_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ back_we(acc_cmd, '0');
set_nz_from_alu;
end if;
a2_abs;
if exec_cycle = T3 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- back_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ back_we(acc_cmd, '0');
set_nz_from_alu;
end if;
a2_abs_xy(true);
if exec_cycle = T3 or exec_cycle = T0 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- back_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ back_we(acc_cmd, '0');
set_nz_from_alu;
end if;
a2_abs_xy(false);
if exec_cycle = T3 or exec_cycle = T0 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- back_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ back_we(acc_cmd, '0');
set_nz_from_alu;
end if;
a2_indir_x;
if exec_cycle = T5 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- back_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ back_we(acc_cmd, '0');
set_nz_from_alu;
end if;
a2_indir_y;
if exec_cycle = T4 or exec_cycle = T0 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- back_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ back_we(acc_cmd, '0');
set_nz_from_alu;
end if;
a2_zp;
if exec_cycle = T2 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
set_nvz_from_alu;
end if;
a2_abs;
if exec_cycle = T3 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
set_nvz_from_alu;
end if;
d_print("cmp");
fetch_imm;
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
set_nzc_from_alu;
elsif instruction = conv_std_logic_vector(16#c5#, dsize) then
a2_zp;
if exec_cycle = T2 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
set_nzc_from_alu;
end if;
a2_zp_xy(true);
if exec_cycle = T3 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
set_nzc_from_alu;
end if;
a2_abs;
if exec_cycle = T3 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
set_nzc_from_alu;
end if;
a2_abs_xy(true);
if exec_cycle = T3 or exec_cycle = T0 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
set_nzc_from_alu;
end if;
a2_abs_xy(false);
if exec_cycle = T3 or exec_cycle = T0 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
set_nzc_from_alu;
end if;
a2_indir_x;
if exec_cycle = T5 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
set_nzc_from_alu;
end if;
a2_indir_y;
if exec_cycle = T4 or exec_cycle = T0 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
set_nzc_from_alu;
end if;
d_print("cpx");
fetch_imm;
arith_en_n <= '0';
- back_oe(wk_x_cmd, '0');
+ back_oe(x_cmd, '0');
set_nzc_from_alu;
elsif instruction = conv_std_logic_vector(16#e4#, dsize) then
a2_zp;
if exec_cycle = T2 then
arith_en_n <= '0';
- back_oe(wk_x_cmd, '0');
+ back_oe(x_cmd, '0');
set_nzc_from_alu;
end if;
a2_abs;
if exec_cycle = T3 then
arith_en_n <= '0';
- back_oe(wk_x_cmd, '0');
+ back_oe(x_cmd, '0');
set_nzc_from_alu;
end if;
d_print("cpy");
fetch_imm;
arith_en_n <= '0';
- back_oe(wk_y_cmd, '0');
+ back_oe(y_cmd, '0');
set_nzc_from_alu;
elsif instruction = conv_std_logic_vector(16#c4#, dsize) then
a2_zp;
if exec_cycle = T2 then
arith_en_n <= '0';
- back_oe(wk_y_cmd, '0');
+ back_oe(y_cmd, '0');
set_nzc_from_alu;
end if;
a2_abs;
if exec_cycle = T3 then
arith_en_n <= '0';
- back_oe(wk_y_cmd, '0');
+ back_oe(y_cmd, '0');
set_nzc_from_alu;
end if;
d_print("eor");
fetch_imm;
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- back_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ back_we(acc_cmd, '0');
set_nz_from_alu;
elsif instruction = conv_std_logic_vector(16#45#, dsize) then
a2_zp;
if exec_cycle = T2 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- back_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ back_we(acc_cmd, '0');
set_nz_from_alu;
end if;
a2_zp_xy(true);
if exec_cycle = T3 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- back_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ back_we(acc_cmd, '0');
set_nz_from_alu;
end if;
a2_abs;
if exec_cycle = T3 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- back_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ back_we(acc_cmd, '0');
set_nz_from_alu;
end if;
a2_abs_xy(true);
if exec_cycle = T3 or exec_cycle = T0 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- back_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ back_we(acc_cmd, '0');
set_nz_from_alu;
end if;
a2_abs_xy(false);
if exec_cycle = T3 or exec_cycle = T0 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- back_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ back_we(acc_cmd, '0');
set_nz_from_alu;
end if;
a2_indir_x;
if exec_cycle = T5 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- back_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ back_we(acc_cmd, '0');
set_nz_from_alu;
end if;
a2_indir_y;
if exec_cycle = T4 or exec_cycle = T0 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- back_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ back_we(acc_cmd, '0');
set_nz_from_alu;
end if;
--imm
d_print("lda");
fetch_imm;
- front_we(wk_acc_cmd, '0');
+ front_we(acc_cmd, '0');
set_nz_from_bus;
elsif instruction = conv_std_logic_vector(16#a5#, dsize) then
d_print("lda");
a2_zp;
if exec_cycle = T2 then
- front_we(wk_acc_cmd, '0');
+ front_we(acc_cmd, '0');
set_nz_from_bus;
end if;
d_print("lda");
a2_zp_xy(true);
if exec_cycle = T3 then
- front_we(wk_acc_cmd, '0');
+ front_we(acc_cmd, '0');
set_nz_from_bus;
end if;
a2_abs;
if exec_cycle = T3 then
set_nz_from_bus;
- front_we(wk_acc_cmd, '0');
+ front_we(acc_cmd, '0');
end if;
elsif instruction = conv_std_logic_vector(16#bd#, dsize) then
a2_abs_xy(true);
if exec_cycle = T3 or exec_cycle = T0 then
--lda.
- front_we(wk_acc_cmd, '0');
+ front_we(acc_cmd, '0');
set_nz_from_bus;
end if;
a2_abs_xy(false);
if exec_cycle = T3 or exec_cycle = T0 then
--lda.
- front_we(wk_acc_cmd, '0');
+ front_we(acc_cmd, '0');
set_nz_from_bus;
end if;
d_print("lda");
a2_indir_x;
if exec_cycle = T5 then
- front_we(wk_acc_cmd, '0');
+ front_we(acc_cmd, '0');
set_nz_from_bus;
end if;
a2_indir_y;
if exec_cycle = T4 or exec_cycle = T0 then
--lda.
- front_we(wk_acc_cmd, '0');
+ front_we(acc_cmd, '0');
set_nz_from_bus;
end if;
d_print("ldx");
fetch_imm;
set_nz_from_bus;
- front_we(wk_x_cmd, '0');
+ front_we(x_cmd, '0');
elsif instruction = conv_std_logic_vector(16#a6#, dsize) then
--zp
d_print("ldx");
a2_zp;
if exec_cycle = T2 then
- front_we(wk_x_cmd, '0');
+ front_we(x_cmd, '0');
set_nz_from_bus;
end if;
d_print("ldx");
a2_zp_xy(false);
if exec_cycle = T3 then
- front_we(wk_x_cmd, '0');
+ front_we(x_cmd, '0');
set_nz_from_bus;
end if;
a2_abs;
if exec_cycle = T3 then
set_nz_from_bus;
- front_we(wk_x_cmd, '0');
+ front_we(x_cmd, '0');
end if;
elsif instruction = conv_std_logic_vector(16#be#, dsize) then
d_print("ldx");
a2_abs_xy(false);
if exec_cycle = T3 or exec_cycle = T0 then
- front_we(wk_x_cmd, '0');
+ front_we(x_cmd, '0');
set_nz_from_bus;
end if;
d_print("ldy");
fetch_imm;
set_nz_from_bus;
- front_we(wk_y_cmd, '0');
+ front_we(y_cmd, '0');
elsif instruction = conv_std_logic_vector(16#a4#, dsize) then
--zp
d_print("ldy");
a2_zp;
if exec_cycle = T2 then
- front_we(wk_y_cmd, '0');
+ front_we(y_cmd, '0');
set_nz_from_bus;
end if;
d_print("ldy");
a2_zp_xy(true);
if exec_cycle = T3 then
- front_we(wk_y_cmd, '0');
+ front_we(y_cmd, '0');
set_nz_from_bus;
end if;
a2_abs;
if exec_cycle = T3 then
set_nz_from_bus;
- front_we(wk_y_cmd, '0');
+ front_we(y_cmd, '0');
end if;
elsif instruction = conv_std_logic_vector(16#bc#, dsize) then
a2_abs_xy(true);
if exec_cycle = T3 or exec_cycle = T0 then
set_nz_from_bus;
- front_we(wk_y_cmd, '0');
+ front_we(y_cmd, '0');
end if;
elsif instruction = conv_std_logic_vector(16#09#, dsize) then
d_print("ora");
fetch_imm;
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- back_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ back_we(acc_cmd, '0');
set_nz_from_alu;
elsif instruction = conv_std_logic_vector(16#05#, dsize) then
a2_zp;
if exec_cycle = T2 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- back_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ back_we(acc_cmd, '0');
set_nz_from_alu;
end if;
a2_zp_xy(true);
if exec_cycle = T3 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- back_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ back_we(acc_cmd, '0');
set_nz_from_alu;
end if;
a2_abs;
if exec_cycle = T3 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- back_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ back_we(acc_cmd, '0');
set_nz_from_alu;
end if;
a2_abs_xy(true);
if exec_cycle = T3 or exec_cycle = T0 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- back_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ back_we(acc_cmd, '0');
set_nz_from_alu;
end if;
a2_abs_xy(false);
if exec_cycle = T3 or exec_cycle = T0 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- back_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ back_we(acc_cmd, '0');
set_nz_from_alu;
end if;
a2_indir_x;
if exec_cycle = T5 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- back_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ back_we(acc_cmd, '0');
set_nz_from_alu;
end if;
a2_indir_y;
if exec_cycle = T4 or exec_cycle = T0 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- back_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ back_we(acc_cmd, '0');
set_nz_from_alu;
end if;
d_print("sbc");
fetch_imm;
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- back_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ back_we(acc_cmd, '0');
set_nvzc_from_alu;
elsif instruction = conv_std_logic_vector(16#e5#, dsize) then
a2_zp;
if exec_cycle = T2 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- back_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ back_we(acc_cmd, '0');
set_nvzc_from_alu;
end if;
a2_zp_xy(true);
if exec_cycle = T3 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- back_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ back_we(acc_cmd, '0');
set_nvzc_from_alu;
end if;
a2_abs;
if exec_cycle = T3 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- back_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ back_we(acc_cmd, '0');
set_nvzc_from_alu;
end if;
a2_abs_xy(true);
if exec_cycle = T3 or exec_cycle = T0 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- back_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ back_we(acc_cmd, '0');
set_nvzc_from_alu;
end if;
a2_abs_xy(false);
if exec_cycle = T3 or exec_cycle = T0 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- back_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ back_we(acc_cmd, '0');
set_nvzc_from_alu;
end if;
a2_indir_x;
if exec_cycle = T5 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- back_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ back_we(acc_cmd, '0');
set_nvzc_from_alu;
end if;
a2_indir_y;
if exec_cycle = T4 or exec_cycle = T0 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- back_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ back_we(acc_cmd, '0');
set_nvzc_from_alu;
end if;
d_print("sta");
a3_zp;
if exec_cycle = T2 then
- front_oe(wk_acc_cmd, '0');
+ front_oe(acc_cmd, '0');
end if;
elsif instruction = conv_std_logic_vector(16#95#, dsize) then
d_print("sta");
a3_zp_xy(true);
if exec_cycle = T2 then
- front_oe(wk_acc_cmd, '0');
+ front_oe(acc_cmd, '0');
end if;
elsif instruction = conv_std_logic_vector(16#8d#, dsize) then
d_print("sta");
a3_abs;
if exec_cycle = T3 then
- front_oe(wk_acc_cmd, '0');
+ front_oe(acc_cmd, '0');
end if;
elsif instruction = conv_std_logic_vector(16#9d#, dsize) then
d_print("sta");
a3_abs_xy (true);
if exec_cycle = T4 then
- front_oe(wk_acc_cmd, '0');
+ front_oe(acc_cmd, '0');
end if;
elsif instruction = conv_std_logic_vector(16#99#, dsize) then
d_print("sta");
a3_abs_xy (false);
if exec_cycle = T4 then
- front_oe(wk_acc_cmd, '0');
+ front_oe(acc_cmd, '0');
end if;
elsif instruction = conv_std_logic_vector(16#81#, dsize) then
d_print("sta");
a3_indir_x;
if exec_cycle = T5 then
- front_oe(wk_acc_cmd, '0');
+ front_oe(acc_cmd, '0');
end if;
elsif instruction = conv_std_logic_vector(16#91#, dsize) then
d_print("sta");
a3_indir_y;
if exec_cycle = T5 then
- front_oe(wk_acc_cmd, '0');
+ front_oe(acc_cmd, '0');
end if;
elsif instruction = conv_std_logic_vector(16#86#, dsize) then
d_print("stx");
a3_zp;
if exec_cycle = T2 then
- front_oe(wk_x_cmd, '0');
+ front_oe(x_cmd, '0');
end if;
elsif instruction = conv_std_logic_vector(16#96#, dsize) then
d_print("stx");
a3_zp_xy(false);
if exec_cycle = T2 then
- front_oe(wk_x_cmd, '0');
+ front_oe(x_cmd, '0');
end if;
elsif instruction = conv_std_logic_vector(16#8e#, dsize) then
d_print("stx");
a3_abs;
if exec_cycle = T3 then
- front_oe(wk_x_cmd, '0');
+ front_oe(x_cmd, '0');
end if;
elsif instruction = conv_std_logic_vector(16#84#, dsize) then
d_print("sty");
a3_zp;
if exec_cycle = T2 then
- front_oe(wk_y_cmd, '0');
+ front_oe(y_cmd, '0');
end if;
elsif instruction = conv_std_logic_vector(16#94#, dsize) then
d_print("sty");
a3_zp_xy(true);
if exec_cycle = T2 then
- front_oe(wk_y_cmd, '0');
+ front_oe(y_cmd, '0');
end if;
elsif instruction = conv_std_logic_vector(16#8c#, dsize) then
d_print("sty");
a3_abs;
if exec_cycle = T3 then
- front_oe(wk_y_cmd, '0');
+ front_oe(y_cmd, '0');
end if;
d_print("pha");
a51_push;
if exec_cycle = T2 then
- front_oe(wk_acc_cmd, '0');
+ front_oe(acc_cmd, '0');
end if;
elsif instruction = conv_std_logic_vector(16#28#, dsize) then
d_print("pla");
a52_pull;
if exec_cycle = T3 then
- front_we(wk_acc_cmd, '0');
+ front_we(acc_cmd, '0');
set_nz_from_bus;
end if;
fetch_next;
dbuf_int_oe_n <= '0';
--latch adl
- dl_al_we_n <= '0';
- wk_next_cycle <= T2;
+ next_cycle <= T2;
elsif exec_cycle = T2 then
d_print("jsr 3");
fetch_stop;
dbuf_int_oe_n <= '1';
- dl_al_we_n <= '1';
--push return addr high into stack.
sp_push_n <= '0';
back_oe(sp_cmd, '0');
back_we(sp_cmd, '0');
r_nw <= '0';
- wk_next_cycle <= T3;
+ next_cycle <= T3;
elsif exec_cycle = T3 then
d_print("jsr 4");
front_oe(pch_cmd, '1');
back_we(sp_cmd, '0');
r_nw <= '0';
- wk_next_cycle <= T4;
+ next_cycle <= T4;
elsif exec_cycle = T4 then
d_print("jsr 5");
sp_push_n <= '1';
back_oe(pch_cmd, '0');
back_oe(pcl_cmd, '0');
dbuf_int_oe_n <= '0';
- dl_ah_we_n <= '0';
+ front_we(idl_h_cmd, '0');
- wk_next_cycle <= T5;
+ next_cycle <= T5;
elsif exec_cycle = T5 then
d_print("jsr 6");
back_oe(pch_cmd, '1');
back_oe(pcl_cmd, '1');
dbuf_int_oe_n <= '1';
- dl_ah_we_n <= '1';
+ front_we(idl_h_cmd, '1');
+
--load/output pch
ad_oe_n <= '1';
- dl_dh_oe_n <= '0';
+ front_oe(idl_h_cmd, '0');
front_we(pch_cmd, '0');
--load pcl.
- dl_al_oe_n <= '0';
+ back_oe(idl_l_cmd, '0');
back_we(pcl_cmd, '0');
- wk_next_cycle <= T0;
+ next_cycle <= T0;
end if; --if exec_cycle = T1 then
-- A.5.4 break
sp_pop_n <= '0';
sp_oe_n <= '0';
- wk_next_cycle <= T2;
+ next_cycle <= T2;
elsif exec_cycle = T2 then
d_print("rti 3");
dbuf_int_oe_n <= '0';
stat_bus_all_n <= '0';
- wk_next_cycle <= T3;
+ next_cycle <= T3;
elsif exec_cycle = T3 then
d_print("rti 4");
stat_bus_all_n <= '1';
dbuf_int_oe_n <= '0';
front_we(pcl_cmd, '0');
- wk_next_cycle <= T4;
+ next_cycle <= T4;
elsif exec_cycle = T4 then
d_print("rti 5");
--stack decrement stop.
dbuf_int_oe_n <= '0';
front_we(pch_cmd, '0');
- wk_next_cycle <= T5;
+ next_cycle <= T5;
elsif exec_cycle = T5 then
d_print("rti 6");
back_oe(sp_cmd, '1');
front_we(pch_cmd, '1');
--increment pc.
- wk_next_cycle <= T0;
+ next_cycle <= T0;
end if; --if exec_cycle = T1 then
----------------------------------------
--latch abs low data.
dbuf_int_oe_n <= '0';
- dl_al_we_n <= '0';
- wk_next_cycle <= T2;
+ next_cycle <= T2;
elsif exec_cycle = T2 then
d_print("jmp 3");
- dl_al_we_n <= '1';
--fetch abs hi
fetch_next;
--latch in dlh
dbuf_int_oe_n <= '0';
- dl_ah_we_n <= '0';
---load pch.
front_we(pch_cmd, '0');
- wk_next_cycle <= T0;
+ next_cycle <= T0;
end if;
elsif instruction = conv_std_logic_vector(16#6c#, dsize) then
--latch abs low data.
dbuf_int_oe_n <= '0';
- dl_al_we_n <= '0';
- wk_next_cycle <= T2;
+ next_cycle <= T2;
elsif exec_cycle = T2 then
d_print("jmp 3");
- dl_al_we_n <= '1';
--fetch abs hi
fetch_next;
--latch in dlh
dbuf_int_oe_n <= '0';
- dl_ah_we_n <= '0';
- wk_next_cycle <= T3;
+ next_cycle <= T3;
elsif exec_cycle = T3 then
fetch_stop;
- dl_ah_we_n <= '1';
--IAH/IAL > ADL
- dl_ah_oe_n <= '0';
- dl_al_oe_n <= '0';
+ back_oe(idl_h_cmd, '0');
+ back_oe(idl_l_cmd, '0');
front_we(pcl_cmd, '0');
- wk_next_cycle <= T4;
+ next_cycle <= T4;
elsif exec_cycle = T4 then
- dl_ah_oe_n <= '0';
- dl_al_oe_n <= '0';
+ back_oe(idl_h_cmd, '0');
+ back_oe(idl_l_cmd, '0');
front_we(pcl_cmd, '1');
--IAH/IAL+1 > ADH
front_we(pch_cmd, '0');
indir_n <= '0';
- wk_next_cycle <= T0;
+ next_cycle <= T0;
end if;
sp_pop_n <= '0';
sp_oe_n <= '0';
- wk_next_cycle <= T2;
+ next_cycle <= T2;
elsif exec_cycle = T2 then
d_print("rts 3");
dbuf_int_oe_n <= '0';
front_we(pcl_cmd, '0');
- wk_next_cycle <= T3;
+ next_cycle <= T3;
elsif exec_cycle = T3 then
d_print("rts 4");
--stack decrement stop.
dbuf_int_oe_n <= '0';
front_we(pch_cmd, '0');
- wk_next_cycle <= T4;
+ next_cycle <= T4;
elsif exec_cycle = T4 then
d_print("rts 5");
back_oe(sp_cmd, '1');
front_we(pch_cmd, '1');
--empty cycle.
--complying h/w manual...
- wk_next_cycle <= T5;
+ next_cycle <= T5;
elsif exec_cycle = T5 then
d_print("rts 6");
--increment pc.
fetch_next;
- wk_next_cycle <= T0;
+ next_cycle <= T0;
end if; --if exec_cycle = T1 then
----------------------------------------
elsif exec_cycle = R0 then
d_print(string'("reset"));
+ init_all_pins;
- --initialize port...
- inst_we_n <= '1';
- ad_oe_n <= '1';
- dbuf_int_oe_n <= '1';
- dl_al_we_n <= '1';
- dl_ah_we_n <= '1';
- dl_al_oe_n <= '1';
- dl_ah_oe_n <= '1';
- dl_dh_oe_n <= '1';
- pcl_inc_n <= '1';
- pcl_cmd <= "1111";
- pch_cmd <= "1111";
- sp_cmd <= "1111";
- sp_oe_n <= '1';
- sp_push_n <= '1';
- sp_pop_n <= '1';
- wk_acc_cmd <= "1111";
- wk_x_cmd <= "1111";
- wk_y_cmd <= "1111";
-
- abs_xy_n <= '1';
- pg_next_n <= '1';
- zp_n <= '1';
- zp_xy_n <= '1';
- rel_calc_n <= '1';
- indir_n <= '1';
- indir_x_n <= '1';
- indir_y_n <= '1';
- arith_en_n <= '1';
-
- stat_dec_oe_n <= '0';
- stat_bus_oe_n <= '1';
- stat_set_flg_n <= '1';
- stat_flg <= '1';
- stat_bus_all_n <= '1';
- stat_bus_nz_n <= '1';
- wk_stat_alu_we_n <= '1';
-
- r_vec_oe_n <= '1';
- n_vec_oe_n <= '1';
- i_vec_oe_n <= '1';
- nmi_handled_n <= '1';
- r_nw <= '1';
-
- wk_next_cycle <= R1;
+ next_cycle <= R1;
elsif exec_cycle = R1 or exec_cycle = N1 then
+ init_all_pins;
+
+ if exec_cycle = R1 then
+ next_cycle <= R2;
+ elsif exec_cycle = N1 then
+ next_cycle <= N2;
+ end if;
+ elsif exec_cycle = R2 or exec_cycle = N2 then
pcl_cmd <= "1111";
pcl_inc_n <= '1';
inst_we_n <= '1';
- dl_al_oe_n <= '1';
+ back_oe(idl_l_cmd, '1');
--push pch.
- d_print("R1");
+ d_print("R2");
ad_oe_n <= '0';
sp_push_n <= '0';
sp_oe_n <= '0';
back_we(sp_cmd, '0');
r_nw <= '0';
- if exec_cycle = R1 then
- wk_next_cycle <= R2;
- elsif exec_cycle = N1 then
- wk_next_cycle <= N2;
+ if exec_cycle = R2 then
+ next_cycle <= R3;
+ elsif exec_cycle = N2 then
+ next_cycle <= N3;
end if;
- elsif exec_cycle = R2 or exec_cycle = N2 then
+ elsif exec_cycle = R3 or exec_cycle = N3 then
front_oe(pch_cmd, '1');
--push pcl.
back_we(sp_cmd, '0');
r_nw <= '0';
- if exec_cycle = R2 then
- wk_next_cycle <= R3;
- elsif exec_cycle = N2 then
- wk_next_cycle <= N3;
+ if exec_cycle = R3 then
+ next_cycle <= R4;
+ elsif exec_cycle = N3 then
+ next_cycle <= N4;
end if;
- elsif exec_cycle = R3 or exec_cycle = N3 then
+ elsif exec_cycle = R4 or exec_cycle = N4 then
front_oe(pcl_cmd, '1');
--push status.
back_we(sp_cmd, '0');
r_nw <= '0';
- if exec_cycle = R3 then
- wk_next_cycle <= R4;
- elsif exec_cycle = N3 then
- wk_next_cycle <= N4;
+ if exec_cycle = R4 then
+ next_cycle <= R5;
+ elsif exec_cycle = N4 then
+ next_cycle <= N5;
end if;
- elsif exec_cycle = R4 or exec_cycle = N4 then
+ elsif exec_cycle = R5 or exec_cycle = N5 then
stat_bus_oe_n <= '1';
sp_push_n <= '1';
sp_oe_n <= '1';
r_nw <= '1';
dbuf_int_oe_n <= '0';
front_we(pcl_cmd, '0');
- dl_al_oe_n <= '1';
- dl_ah_oe_n <= '1';
+ back_oe(idl_l_cmd, '1');
+ back_oe(idl_h_cmd, '1');
- if exec_cycle = R4 then
+ if exec_cycle = R5 then
r_vec_oe_n <= '0';
n_vec_oe_n <= '1';
- wk_next_cycle <= R5;
- elsif exec_cycle = N4 then
+ next_cycle <= R6;
+ elsif exec_cycle = N5 then
r_vec_oe_n <= '1';
n_vec_oe_n <= '0';
- wk_next_cycle <= N5;
+ next_cycle <= N6;
end if;
- elsif exec_cycle = R5 or exec_cycle = N5 then
+ elsif exec_cycle = R6 or exec_cycle = N6 then
front_we(pcl_cmd, '1');
--fetch reset vector hi
front_we(pch_cmd, '0');
indir_n <= '0';
- if exec_cycle = N5 then
+ if exec_cycle = N6 then
nmi_handled_n <= '0';
end if;
--start execute cycle.
- wk_next_cycle <= T0;
-
- elsif exec_cycle(5) = '1' then
- ---pc increment and next page.
- d_print(string'("pch next page..."));
- --pcl stop increment
- pcl_inc_n <= '1';
- back_we(pcl_cmd, '1');
-
- if ('0' & exec_cycle(4 downto 0) = T0 and
- instruction = conv_std_logic_vector(16#4c#, dsize) ) then
- --jmp instruction t0 cycle discards pch increment.
- back_we(pch_cmd, '1');
- front_we(pch_cmd, '1');
- else
- --pch increment
- back_we(pch_cmd, '0');
- back_oe(pch_cmd, '0');
- end if;
-
- if ('0' & exec_cycle(4 downto 0) = T0) then
- --do the t0 identical routine.
- disable_pins;
- inst_we_n <= '1';
- r_nw <= '1';
-
- elsif ('0' & exec_cycle(4 downto 0) = T1) then
- --if fetch cycle, preserve instrution register
- inst_we_n <= '1';
-
- elsif ('0' & exec_cycle(4 downto 0) = T2) then
- --disable previous we_n gate.
- --t1 cycle is fetch low oprand.
- dl_al_we_n <= '1';
- dl_ah_we_n <= '1';
- elsif ('0' & exec_cycle(4 downto 0) = T3) then
- --t2 cycle is fetch high oprand.
- dl_ah_we_n <= '1';
- end if;
+ next_cycle <= T0;
end if; --if rdy = '0' then
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