vram latch addr output timing changed

[motonesfpga/motonesfpga.git] / de1_nes / ppu / ppu_registers.vhd

diff --git a/de1_nes/ppu/ppu_registers.vhd b/de1_nes/ppu/ppu_registers.vhd
index 6764f16..338ebfd 100644 (file)
--- a/de1_nes/ppu/ppu_registers.vhd
+++ b/de1_nes/ppu/ppu_registers.vhd
@@ -103,8 +103,8 @@ component tri_state_buffer
         );\r
 end component;\r
 
-signal d_in, q_out : std_logic_vector(13 downto 0);\r
-signal we_n, oe_n : std_logic;\r
+signal d_in         : std_logic_vector(13 downto 0);\r
+signal we_n, oe_n   : std_logic;\r
 
 begin\r
     dbg_vl_we_n <= we_n;\r
@@ -115,8 +115,6 @@ begin
     oe_n <= '0' when ale = '0' else\r
             '1';\r
     out_reg_inst : d_flip_flop generic map (14)\r
-            port map (clk, rst_n, '1', we_n, d_in, q_out);\r
-    out_tss_inst : tri_state_buffer generic map (14)\r
-            port map (oe_n, q_out, v_addr);\r
+            port map (clk, rst_n, '1', we_n, d_in, v_addr);\r
 end rtl;