android: AMDGPU/GlobalISel: fix tablegen rules (llvm90)

[android-x86/external-llvm.git] / docs / AMDGPUUsage.rst

diff --git a/docs/AMDGPUUsage.rst b/docs/AMDGPUUsage.rst
index e035c62..fc624a7 100644 (file)
--- a/docs/AMDGPUUsage.rst
+++ b/docs/AMDGPUUsage.rst
@@ -207,6 +207,10 @@ names from both the *Processor* and *Alternative Processor* can be used.
                                                                                  names.
      ``gfx906``                  ``amdgcn``   dGPU  - xnack                   - Radeon Instinct MI50
                                                       [off]                   - Radeon Instinct MI60
+     ``gfx908``                  ``amdgcn``   dGPU  - xnack                   *TBA*
+                                                      [off]
+                                                      sram-ecc
+                                                      [on]
      ``gfx909``                  ``amdgcn``   APU   - xnack                   *TBA* (Raven Ridge 2)
                                                       [on]
                                                                               .. TODO
@@ -674,7 +678,7 @@ The AMDGPU backend uses the following ELF header:
      ``EF_AMDGPU_MACH_AMDGCN_GFX902``  0x02d      ``gfx902``
      ``EF_AMDGPU_MACH_AMDGCN_GFX904``  0x02e      ``gfx904``
      ``EF_AMDGPU_MACH_AMDGCN_GFX906``  0x02f      ``gfx906``
-     *reserved*                        0x030      Reserved.
+     ``EF_AMDGPU_MACH_AMDGCN_GFX908``  0x030      ``gfx908``
      ``EF_AMDGPU_MACH_AMDGCN_GFX909``  0x031      ``gfx909``
      *reserved*                        0x032      Reserved.
      ``EF_AMDGPU_MACH_AMDGCN_GFX1010`` 0x033      ``gfx1010``
@@ -1391,6 +1395,11 @@ non-AMD key names should be prefixed by "*vendor-name*.".
                                                   the ancestor tree for determining
                                                   when the parent kernel has finished.
 
+                                                "HiddenMultiGridSyncArg"
+                                                  A global address space pointer for
+                                                  multi-grid synchronization is
+                                                  passed in the kernarg.
+
      "ValueType"       string         Required  Kernel argument value type. Only
                                                 present if "ValueKind" is
                                                 "ByValue". For vector data
@@ -1880,6 +1889,11 @@ same *vendor-name*.
                                                        the ancestor tree for determining
                                                        when the parent kernel has finished.
 
+                                                     "hidden_multigrid_sync_arg"
+                                                       A global address space pointer for
+                                                       multi-grid synchronization is
+                                                       passed in the kernarg.
+
      ".value_type"          string         Required  Kernel argument value type. Only
                                                      present if ".value_kind" is
                                                      "by_value". For vector data
@@ -5696,6 +5710,8 @@ When the language is OpenCL the following differences occur:
                              enqueue_kernel.
      6        8    8         OpenCL address of AqlWrap struct used by
                              enqueue_kernel.
+     7        8    8         Pointer argument used for Multi-gird
+                             synchronization.
      ======== ==== ========= ===========================================
 
 .. _amdgpu-hcc:
@@ -5726,14 +5742,12 @@ Instructions
    AMDGPU/AMDGPUAsmGFX7
    AMDGPU/AMDGPUAsmGFX8
    AMDGPU/AMDGPUAsmGFX9
+   AMDGPU/AMDGPUAsmGFX10
    AMDGPUModifierSyntax
    AMDGPUOperandSyntax
    AMDGPUInstructionSyntax
    AMDGPUInstructionNotation
 
-.. TODO
-   AMDGPUAsmGFX10
-
 An instruction has the following :doc:`syntax<AMDGPUInstructionSyntax>`:
 
     ``<``\ *opcode*\ ``>    <``\ *operand0*\ ``>, <``\ *operand1*\ ``>,...    <``\ *modifier0*\ ``> <``\ *modifier1*\ ``>...``
@@ -5745,7 +5759,8 @@ The order of *operands* and *modifiers* is fixed.
 Most *modifiers* are optional and may be omitted.
 
 See detailed instruction syntax description for :doc:`GFX7<AMDGPU/AMDGPUAsmGFX7>`,
-:doc:`GFX8<AMDGPU/AMDGPUAsmGFX8>` and :doc:`GFX9<AMDGPU/AMDGPUAsmGFX9>`.
+:doc:`GFX8<AMDGPU/AMDGPUAsmGFX8>`, :doc:`GFX9<AMDGPU/AMDGPUAsmGFX9>`
+and :doc:`GFX10<AMDGPU/AMDGPUAsmGFX10>`.
 
 Note that features under development are not included in this description.