drm/amdgpu: fix amdgpu_irq_put call trace in gmc_v10_0_hw_fini

[tomoyo/tomoyo-test1.git] / drivers / gpu / drm / amd / amdgpu / gmc_v10_0.c

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index 7db1f1a..b213dcf 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -479,8 +479,8 @@ static int gmc_v10_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
 static uint64_t gmc_v10_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
                                             unsigned vmid, uint64_t pd_addr)
 {
-       bool use_semaphore = gmc_v10_0_use_invalidate_semaphore(ring->adev, ring->funcs->vmhub);
-       struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
+       bool use_semaphore = gmc_v10_0_use_invalidate_semaphore(ring->adev, ring->vm_hub);
+       struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub];
        uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0);
        unsigned eng = ring->vm_inv_eng;
 
@@ -534,7 +534,7 @@ static void gmc_v10_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid
        if (ring->is_mes_queue)
                return;
 
-       if (ring->funcs->vmhub == AMDGPU_GFXHUB_0)
+       if (ring->vm_hub == AMDGPU_GFXHUB_0)
                reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid;
        else
                reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;
@@ -692,31 +692,15 @@ static void gmc_v10_0_set_umc_funcs(struct amdgpu_device *adev)
                adev->umc.channel_inst_num = UMC_V8_7_CHANNEL_INSTANCE_NUM;
                adev->umc.umc_inst_num = UMC_V8_7_UMC_INSTANCE_NUM;
                adev->umc.channel_offs = UMC_V8_7_PER_CHANNEL_OFFSET_SIENNA;
+               adev->umc.retire_unit = 1;
                adev->umc.channel_idx_tbl = &umc_v8_7_channel_idx_tbl[0][0];
                adev->umc.ras = &umc_v8_7_ras;
                break;
        default:
                break;
        }
-       if (adev->umc.ras) {
-               amdgpu_ras_register_ras_block(adev, &adev->umc.ras->ras_block);
-
-               strcpy(adev->umc.ras->ras_block.ras_comm.name, "umc");
-               adev->umc.ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__UMC;
-               adev->umc.ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
-               adev->umc.ras_if = &adev->umc.ras->ras_block.ras_comm;
-
-               /* If don't define special ras_late_init function, use default ras_late_init */
-               if (!adev->umc.ras->ras_block.ras_late_init)
-                               adev->umc.ras->ras_block.ras_late_init = amdgpu_umc_ras_late_init;
-
-               /* If not defined special ras_cb function, use default ras_cb */
-               if (!adev->umc.ras->ras_block.ras_cb)
-                       adev->umc.ras->ras_block.ras_cb = amdgpu_umc_process_ras_data_cb;
-       }
 }
 
-
 static void gmc_v10_0_set_mmhub_funcs(struct amdgpu_device *adev)
 {
        switch (adev->ip_versions[MMHUB_HWIP][0]) {
@@ -753,7 +737,6 @@ static void gmc_v10_0_set_gfxhub_funcs(struct amdgpu_device *adev)
 
 static int gmc_v10_0_early_init(void *handle)
 {
-       int r;
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
        gmc_v10_0_set_mmhub_funcs(adev);
@@ -769,10 +752,6 @@ static int gmc_v10_0_early_init(void *handle)
        adev->gmc.private_aperture_end =
                adev->gmc.private_aperture_start + (4ULL << 30) - 1;
 
-       r = amdgpu_gmc_ras_early_init(adev);
-       if (r)
-               return r;
-
        return 0;
 }
 
@@ -1023,6 +1002,10 @@ static int gmc_v10_0_sw_init(void *handle)
 
        amdgpu_vm_manager_init(adev);
 
+       r = amdgpu_gmc_ras_sw_init(adev);
+       if (r)
+               return r;
+
        return 0;
 }
 
@@ -1160,7 +1143,6 @@ static int gmc_v10_0_hw_fini(void *handle)
                return 0;
        }
 
-       amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0);
        amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
 
        return 0;