Merge "msm/drm: Move msm_drm_config configuration into the GPUs"

[sagit-ice-cold/kernel_xiaomi_msm8998.git] / drivers / gpu / drm / msm / adreno / adreno_gpu.c

diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index 19267b2..9952fa8 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -405,10 +405,6 @@ void adreno_wait_ring(struct msm_ringbuffer *ring, uint32_t ndwords)
                        ring->gpu->name, ring->id);
 }
 
-static const char *iommu_ports[] = {
-               "gfx3d_user",
-};
-
 /* Read the set of powerlevels */
 static int _adreno_get_pwrlevels(struct msm_gpu *gpu, struct device_node *node)
 {
@@ -524,10 +520,10 @@ static int adreno_of_parse(struct platform_device *pdev, struct msm_gpu *gpu)
 
 int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
                struct adreno_gpu *adreno_gpu,
-               const struct adreno_gpu_funcs *funcs, int nr_rings)
+               const struct adreno_gpu_funcs *funcs,
+               struct msm_gpu_config *gpu_config)
 {
        struct adreno_platform_config *config = pdev->dev.platform_data;
-       struct msm_gpu_config adreno_gpu_config  = { 0 };
        struct msm_gpu *gpu = &adreno_gpu->base;
        struct msm_mmu *mmu;
        int ret;
@@ -541,26 +537,8 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
        /* Get the rest of the target configuration from the device tree */
        adreno_of_parse(pdev, gpu);
 
-       adreno_gpu_config.ioname = "kgsl_3d0_reg_memory";
-       adreno_gpu_config.irqname = "kgsl_3d0_irq";
-       adreno_gpu_config.nr_rings = nr_rings;
-
-       adreno_gpu_config.va_start = SZ_16M;
-       adreno_gpu_config.va_end = 0xffffffff;
-
-       if (adreno_gpu->revn >= 500) {
-               /* 5XX targets use a 64 bit region */
-               adreno_gpu_config.va_start = 0x800000000;
-               adreno_gpu_config.va_end = 0x8ffffffff;
-       } else {
-               adreno_gpu_config.va_start = 0x300000;
-               adreno_gpu_config.va_end = 0xffffffff;
-       }
-
-       adreno_gpu_config.nr_rings = nr_rings;
-
        ret = msm_gpu_init(drm, pdev, &adreno_gpu->base, &funcs->base,
-                       adreno_gpu->info->name, &adreno_gpu_config);
+                       adreno_gpu->info->name, gpu_config);
        if (ret)
                return ret;
 
@@ -580,8 +558,7 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
 
        mmu = gpu->aspace->mmu;
        if (mmu) {
-               ret = mmu->funcs->attach(mmu, iommu_ports,
-                               ARRAY_SIZE(iommu_ports));
+               ret = mmu->funcs->attach(mmu, NULL, 0);
                if (ret)
                        return ret;
        }
@@ -722,7 +699,7 @@ static struct adreno_counter_group *get_counter_group(struct msm_gpu *gpu,
                return ERR_PTR(-ENODEV);
 
        if (groupid >= adreno_gpu->nr_counter_groups)
-               return ERR_PTR(-EINVAL);
+               return ERR_PTR(-ENODEV);
 
        return (struct adreno_counter_group *)
                adreno_gpu->counter_groups[groupid];
@@ -745,7 +722,7 @@ u64 adreno_read_counter(struct msm_gpu *gpu, u32 groupid, int counterid)
        struct adreno_counter_group *group =
                get_counter_group(gpu, groupid);
 
-       if (!IS_ERR(group) && group->funcs.read)
+       if (!IS_ERR_OR_NULL(group) && group->funcs.read)
                return group->funcs.read(gpu, group, counterid);
 
        return 0;
@@ -756,6 +733,6 @@ void adreno_put_counter(struct msm_gpu *gpu, u32 groupid, int counterid)
        struct adreno_counter_group *group =
                get_counter_group(gpu, groupid);
 
-       if (!IS_ERR(group) && group->funcs.put)
+       if (!IS_ERR_OR_NULL(group) && group->funcs.put)
                group->funcs.put(gpu, group, counterid);
 }