Merge tag 'iommu-updates-v5.14' of git://git.kernel.org/pub/scm/linux/kernel/git...

[uclinux-h8/linux.git] / drivers / iommu / arm / arm-smmu / arm-smmu-qcom.c

diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
index 7771d40..9b9d13e 100644 (file)
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
@@ -14,6 +14,7 @@ struct qcom_smmu {
        struct arm_smmu_device smmu;
        bool bypass_quirk;
        u8 bypass_cbndx;
+       u32 stall_enabled;
 };
 
 static struct qcom_smmu *to_qcom_smmu(struct arm_smmu_device *smmu)
@@ -24,15 +25,61 @@ static struct qcom_smmu *to_qcom_smmu(struct arm_smmu_device *smmu)
 static void qcom_adreno_smmu_write_sctlr(struct arm_smmu_device *smmu, int idx,
                u32 reg)
 {
+       struct qcom_smmu *qsmmu = to_qcom_smmu(smmu);
+
        /*
         * On the GPU device we want to process subsequent transactions after a
         * fault to keep the GPU from hanging
         */
        reg |= ARM_SMMU_SCTLR_HUPCF;
 
+       if (qsmmu->stall_enabled & BIT(idx))
+               reg |= ARM_SMMU_SCTLR_CFCFG;
+
        arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, reg);
 }
 
+static void qcom_adreno_smmu_get_fault_info(const void *cookie,
+               struct adreno_smmu_fault_info *info)
+{
+       struct arm_smmu_domain *smmu_domain = (void *)cookie;
+       struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
+       struct arm_smmu_device *smmu = smmu_domain->smmu;
+
+       info->fsr = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSR);
+       info->fsynr0 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSYNR0);
+       info->fsynr1 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSYNR1);
+       info->far = arm_smmu_cb_readq(smmu, cfg->cbndx, ARM_SMMU_CB_FAR);
+       info->cbfrsynra = arm_smmu_gr1_read(smmu, ARM_SMMU_GR1_CBFRSYNRA(cfg->cbndx));
+       info->ttbr0 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_TTBR0);
+       info->contextidr = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_CONTEXTIDR);
+}
+
+static void qcom_adreno_smmu_set_stall(const void *cookie, bool enabled)
+{
+       struct arm_smmu_domain *smmu_domain = (void *)cookie;
+       struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
+       struct qcom_smmu *qsmmu = to_qcom_smmu(smmu_domain->smmu);
+
+       if (enabled)
+               qsmmu->stall_enabled |= BIT(cfg->cbndx);
+       else
+               qsmmu->stall_enabled &= ~BIT(cfg->cbndx);
+}
+
+static void qcom_adreno_smmu_resume_translation(const void *cookie, bool terminate)
+{
+       struct arm_smmu_domain *smmu_domain = (void *)cookie;
+       struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
+       struct arm_smmu_device *smmu = smmu_domain->smmu;
+       u32 reg = 0;
+
+       if (terminate)
+               reg |= ARM_SMMU_RESUME_TERMINATE;
+
+       arm_smmu_cb_write(smmu, cfg->cbndx, ARM_SMMU_CB_RESUME, reg);
+}
+
 #define QCOM_ADRENO_SMMU_GPU_SID 0
 
 static bool qcom_adreno_smmu_is_gpu_device(struct device *dev)
@@ -168,6 +215,9 @@ static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain,
        priv->cookie = smmu_domain;
        priv->get_ttbr1_cfg = qcom_adreno_smmu_get_ttbr1_cfg;
        priv->set_ttbr0_cfg = qcom_adreno_smmu_set_ttbr0_cfg;
+       priv->get_fault_info = qcom_adreno_smmu_get_fault_info;
+       priv->set_stall = qcom_adreno_smmu_set_stall;
+       priv->resume_translation = qcom_adreno_smmu_resume_translation;
 
        return 0;
 }