Merge MTD 4.3-rc updates into -next

[sagit-ice-cold/kernel_xiaomi_msm8998.git] / drivers / mtd / nand / sunxi_nand.c

diff --git a/drivers/mtd/nand/sunxi_nand.c b/drivers/mtd/nand/sunxi_nand.c
index e7d333c..ef1fe61 100644 (file)
--- a/drivers/mtd/nand/sunxi_nand.c
+++ b/drivers/mtd/nand/sunxi_nand.c
@@ -970,17 +970,23 @@ static int sunxi_nand_chip_init_timings(struct sunxi_nand_chip *chip,
                mode = chip->nand.onfi_timing_mode_default;
        } else {
                uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {};
+               int i;
 
                mode = fls(mode) - 1;
                if (mode < 0)
                        mode = 0;
 
                feature[0] = mode;
-               ret = chip->nand.onfi_set_features(&chip->mtd, &chip->nand,
+               for (i = 0; i < chip->nsels; i++) {
+                       chip->nand.select_chip(&chip->mtd, i);
+                       ret = chip->nand.onfi_set_features(&chip->mtd,
+                                               &chip->nand,
                                                ONFI_FEATURE_ADDR_TIMING_MODE,
                                                feature);
-               if (ret)
-                       return ret;
+                       chip->nand.select_chip(&chip->mtd, -1);
+                       if (ret)
+                               return ret;
+               }
        }
 
        timings = onfi_async_timing_mode_to_sdr_timings(mode);
@@ -1154,16 +1160,9 @@ static int sunxi_nand_ecc_init(struct mtd_info *mtd, struct nand_ecc_ctrl *ecc,
                               struct device_node *np)
 {
        struct nand_chip *nand = mtd->priv;
-       int strength;
-       int blk_size;
        int ret;
 
-       blk_size = of_get_nand_ecc_step_size(np);
-       strength = of_get_nand_ecc_strength(np);
-       if (blk_size > 0 && strength > 0) {
-               ecc->size = blk_size;
-               ecc->strength = strength;
-       } else {
+       if (!ecc->size) {
                ecc->size = nand->ecc_step_ds;
                ecc->strength = nand->ecc_strength_ds;
        }
@@ -1171,12 +1170,6 @@ static int sunxi_nand_ecc_init(struct mtd_info *mtd, struct nand_ecc_ctrl *ecc,
        if (!ecc->size || !ecc->strength)
                return -EINVAL;
 
-       ecc->mode = NAND_ECC_HW;
-
-       ret = of_get_nand_ecc_mode(np);
-       if (ret >= 0)
-               ecc->mode = ret;
-
        switch (ecc->mode) {
        case NAND_ECC_SOFT_BCH:
                break;
@@ -1302,15 +1295,18 @@ static int sunxi_nand_chip_init(struct device *dev, struct sunxi_nfc *nfc,
        /* Default tR value specified in the ONFI spec (chapter 4.15.1) */
        nand->chip_delay = 200;
        nand->controller = &nfc->controller;
+       /*
+        * Set the ECC mode to the default value in case nothing is specified
+        * in the DT.
+        */
+       nand->ecc.mode = NAND_ECC_HW;
+       nand->flash_node = np;
        nand->select_chip = sunxi_nfc_select_chip;
        nand->cmd_ctrl = sunxi_nfc_cmd_ctrl;
        nand->read_buf = sunxi_nfc_read_buf;
        nand->write_buf = sunxi_nfc_write_buf;
        nand->read_byte = sunxi_nfc_read_byte;
 
-       if (of_get_nand_on_flash_bbt(np))
-               nand->bbt_options |= NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB;
-
        mtd = &chip->mtd;
        mtd->dev.parent = dev;
        mtd->priv = nand;
@@ -1320,6 +1316,9 @@ static int sunxi_nand_chip_init(struct device *dev, struct sunxi_nfc *nfc,
        if (ret)
                return ret;
 
+       if (nand->bbt_options & NAND_BBT_USE_FLASH)
+               nand->bbt_options |= NAND_BBT_NO_OOB;
+
        ret = sunxi_nand_chip_init_timings(chip, np);
        if (ret) {
                dev_err(dev, "could not configure chip timings: %d\n", ret);