net: hns3: merge some repetitive macros

[uclinux-h8/linux.git] / drivers / net / ethernet / hisilicon / hns3 / hns3pf / hclge_cmd.h

diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
index 8e5be12..afca9ee 100644 (file)
--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
@@ -9,6 +9,7 @@
 #include "hnae3.h"
 
 #define HCLGE_CMDQ_TX_TIMEOUT          30000
+#define HCLGE_CMDQ_CLEAR_WAIT_TIME     200
 #define HCLGE_DESC_DATA_LEN            6
 
 struct hclge_dev;
@@ -270,6 +271,9 @@ enum hclge_opcode_type {
        /* Led command */
        HCLGE_OPC_LED_STATUS_CFG        = 0xB000,
 
+       /* clear hardware resource command */
+       HCLGE_OPC_CLEAR_HW_RESOURCE     = 0x700B,
+
        /* NCL config command */
        HCLGE_OPC_QUERY_NCL_CONFIG      = 0x7011,
 
@@ -1013,16 +1017,6 @@ struct hclge_common_lb_cmd {
 
 #define HCLGE_TYPE_CRQ                 0
 #define HCLGE_TYPE_CSQ                 1
-#define HCLGE_NIC_CSQ_BASEADDR_L_REG   0x27000
-#define HCLGE_NIC_CSQ_BASEADDR_H_REG   0x27004
-#define HCLGE_NIC_CSQ_DEPTH_REG                0x27008
-#define HCLGE_NIC_CSQ_TAIL_REG         0x27010
-#define HCLGE_NIC_CSQ_HEAD_REG         0x27014
-#define HCLGE_NIC_CRQ_BASEADDR_L_REG   0x27018
-#define HCLGE_NIC_CRQ_BASEADDR_H_REG   0x2701c
-#define HCLGE_NIC_CRQ_DEPTH_REG                0x27020
-#define HCLGE_NIC_CRQ_TAIL_REG         0x27024
-#define HCLGE_NIC_CRQ_HEAD_REG         0x27028
 
 /* this bit indicates that the driver is ready for hardware reset */
 #define HCLGE_NIC_SW_RST_RDY_B         16
@@ -1197,6 +1191,19 @@ struct hclge_dev_specs_1_cmd {
        u8 rsv1[18];
 };
 
+/* mac speed type defined in firmware command */
+enum HCLGE_FIRMWARE_MAC_SPEED {
+       HCLGE_FW_MAC_SPEED_1G,
+       HCLGE_FW_MAC_SPEED_10G,
+       HCLGE_FW_MAC_SPEED_25G,
+       HCLGE_FW_MAC_SPEED_40G,
+       HCLGE_FW_MAC_SPEED_50G,
+       HCLGE_FW_MAC_SPEED_100G,
+       HCLGE_FW_MAC_SPEED_10M,
+       HCLGE_FW_MAC_SPEED_100M,
+       HCLGE_FW_MAC_SPEED_200G,
+};
+
 #define HCLGE_PHY_LINK_SETTING_BD_NUM          2
 
 struct hclge_phy_link_ksetting_0_cmd {