return 0;
}
+static int ipa3_clkon_cfg_wa(void)
+{
+ struct ipahal_reg_clkon_cfg clkon_cfg = { 0 };
+ int ret = 0;
+
+ clkon_cfg.cgc_open_misc = 1;
+
+ if (ipa3_cfg_clkon_cfg(&clkon_cfg)) {
+ IPAERR("fail to set cgc_open_misc = 1\n");
+ ret = -EPERM;
+ }
+
+ return ret;
+}
+
static int ipa3_setup_exception_path(void)
{
struct ipa_ioc_add_hdr *hdr;
ipa3_trigger_ipa_ready_cbs();
complete_all(&ipa3_ctx->init_completion_obj);
- pr_info("IPA driver initialization was successful.\n");
+ /* WA to disable MISC clock gating for IPA_HW_v3_1 */
+ if (ipa3_ctx->ipa_hw_type == IPA_HW_v3_1) {
+ pr_info(" WA to set cgc_open_misc = 1\n");
+ ipa3_clkon_cfg_wa();
+ }
+
+ pr_info("IPA driver initialization was successful\n");
return 0;
fail_teth_bridge_driver_init: