+2006-02-27 Carlos O'Donell <carlos@codesourcery.com>
+
+ * doc/Makefile.am: Add html target.
+ * doc/Makefile.in: Regenerate.
+ * po/Make-in: Add html target.
+
+2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
+
+ * gas/config/tc-i386.c (output_insn): Support Intel Merom New
+ Instructions.
+
+ * gas/config/tc-i386.h (CpuMNI): New.
+ (CpuUnknownFlags): Add CpuMNI.
+
+2006-02-24 David S. Miller <davem@sunset.davemloft.net>
+
+ * config/tc-sparc.c (priv_reg_table): Add entry for "gl".
+ (hpriv_reg_table): New table for hyperprivileged registers.
+ (sparc_ip): New cases '$' and '%' for wrhpr/rdhpr hyperprivileged
+ register encoding.
+
+2006-02-24 DJ Delorie <dj@redhat.com>
+
+ * config/tc-m32c.h (md_apply_fix): Define to m32c_apply_fix.
+ (tc_gen_reloc): Don't define.
+ * config/tc-m32c.c (rl_for, relaxable): New convenience macros.
+ (OPTION_LINKRELAX): New.
+ (md_longopts): Add it.
+ (m32c_relax): New.
+ (md_parse_options): Set it.
+ (md_assemble): Emit relaxation relocs as needed.
+ (md_convert_frag): Emit relaxation relocs as needed.
+ (md_cgen_lookup_reloc): Add LAB_8_8 and LAB_8_16.
+ (m32c_apply_fix): New.
+ (tc_gen_reloc): New.
+ (m32c_force_relocation): Force out jump relocs when relaxing.
+ (m32c_fix_adjustable): Return false if relaxing.
+
+2006-02-24 Paul Brook <paul@codesourcery.com>
+
+ * config/arm/tc-arm.c (arm_ext_v6_notm, arm_ext_div, arm_ext_v7,
+ arm_ext_v7a, arm_ext_v7r, arm_ext_v7m): New variables.
+ (struct asm_barrier_opt): Define.
+ (arm_v7m_psr_hsh, arm_barrier_opt_hsh): New variables.
+ (parse_psr): Accept V7M psr names.
+ (parse_barrier): New function.
+ (enum operand_parse_code): Add OP_oBARRIER.
+ (parse_operands): Implement OP_oBARRIER.
+ (do_barrier): New function.
+ (do_dbg, do_pli, do_t_barrier, do_t_dbg, do_t_div): New functions.
+ (do_t_cpsi): Add V7M restrictions.
+ (do_t_mrs, do_t_msr): Validate V7M variants.
+ (md_assemble): Check for NULL variants.
+ (v7m_psrs, barrier_opt_names): New tables.
+ (insns): Add V7 instructions. Mark V6 instructions absent from V7M.
+ (md_begin): Initialize arm_v7m_psr_hsh and arm_barrier_opt_hsh.
+ (arm_cpu_option_table): Add Cortex-M3, R4 and A8.
+ (arm_arch_option_table): Add armv7, armv7a, armv7r and armv7m.
+ (struct cpu_arch_ver_table): Define.
+ (cpu_arch_ver): New.
+ (aeabi_set_public_attributes): Use cpu_arch_ver. Set
+ Tag_CPU_arch_profile.
+ * doc/c-arm.texi: Document new cpu and arch options.
+
+2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-ia64.c (operand_match): Handle IA64_OPND_IMMU5b.
+
+2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-ia64.c: Update copyright years.
+
+2006-02-22 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-ia64.c (specify_resource): Add the rule 17 from
+ SDM 2.2.
+
+2005-02-22 Paul Brook <paul@codesourcery.com>
+
+ * config/tc-arm.c (do_pld): Remove incorrect write to
+ inst.instruction.
+ (encode_thumb32_addr_mode): Use correct operand.
+
+2006-02-21 Paul Brook <paul@codesourcery.com>
+
+ * config/tc-arm.c (md_apply_fix): Fix off-by-one errors.
+
+2006-02-17 Shrirang Khisti <shrirangk@kpitcummins.com>
+ Anil Paranjape <anilp1@kpitcummins.com>
+ Shilin Shakti <shilins@kpitcummins.com>
+
+ * Makefile.am: Add xc16x related entry.
+ * Makefile.in: Regenerate.
+ * configure.in: Added xc16x related entry.
+ * configure: Regenerate.
+ * config/tc-xc16x.h: New file
+ * config/tc-xc16x.c: New file
+ * doc/c-xc16x.texi: New file for xc16x
+ * doc/all.texi: Entry for xc16x
+ * doc/Makefile.texi: Added c-xc16x.texi
+ * NEWS: Announce the support for the new target.
+
+2006-02-16 Nick Hudson <nick.hudson@dsl.pipex.com>
+
+ * configure.tgt: set emulation for mips-*-netbsd*
+
+2006-02-14 Jakub Jelinek <jakub@redhat.com>
+
+ * config.in: Rebuilt.
+
+2006-02-13 Bob Wilson <bob.wilson@acm.org>
+
+ * config/tc-xtensa.c (xg_add_opcode_fix): Number operands starting
+ from 1, not 0, in error messages.
+ (md_assemble): Simplify special-case check for ENTRY instructions.
+ (tinsn_has_invalid_symbolic_operands): Do not include opcode and
+ operand in error message.
+
+2006-02-13 Joseph S. Myers <joseph@codesourcery.com>
+
+ * configure.tgt (arm-*-linux-gnueabi*): Change to
+ arm-*-linux-*eabi*.
+
+2006-02-10 Nick Clifton <nickc@redhat.com>
+
+ * config/tc-crx.c (check_range): Ensure that the sign bit of a
+ 32-bit value is propagated into the upper bits of a 64-bit long.
+
+ * config/tc-arc.c (init_opcode_tables): Fix cast.
+ (arc_extoper, md_operand): Likewise.
+
+2006-02-09 David Heine <dlheine@tensilica.com>
+
+ * config/tc-xtensa.c (xg_assembly_relax): Increment steps_taken for
+ each relaxation step.
+
+2006-02-09 Eric Botcazou <ebotcazou@libertysurf.fr>
+
+ * configure.in (CHECK_DECLS): Add vsnprintf.
+ * configure: Regenerate.
+ * messages.c (errno.h, stdarg.h, varargs.h, va_list): Do not
+ include/declare here, but...
+ * as.h: Move code detecting VARARGS idiom to the top.
+ (errno.h, stdarg.h, varargs.h, va_list): ...here.
+ (vsnprintf): Declare if not already declared.
+
+2006-02-08 H.J. Lu <hongjiu.lu@intel.com>
+
+ * as.c (close_output_file): New.
+ (main): Register close_output_file with xatexit before
+ dump_statistics. Don't call output_file_close.
+
+2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
+
+ * config/tc-m68k.c (mcf5208_control_regs, mcf5213_control_regs,
+ mcf5329_control_regs): New.
+ (not_current_architecture, selected_arch, selected_cpu): New.
+ (m68k_archs, m68k_extensions): New.
+ (archs): Renamed to ...
+ (m68k_cpus): ... here. Adjust.
+ (n_arches): Remove.
+ (md_pseudo_table): Add arch and cpu directives.
+ (find_cf_chip, m68k_ip): Adjust table scanning.
+ (no_68851, no_68881): Remove.
+ (md_assemble): Lazily initialize.
+ (select_control_regs): Adjust cpu names. Add 5208, 5213, 5329.
+ (md_init_after_args): Move functionality to m68k_init_arch.
+ (mri_chip): Adjust table scanning.
+ (md_parse_option): Reimplement 'm' processing to add -march & -mcpu
+ options with saner parsing.
+ (m68k_lookup_cpu, m68k_set_arch, m68k_set_cpu, m68k_set_extension,
+ m68k_init_arch): New.
+ (s_m68k_cpu, s_m68k_arch): New.
+ (md_show_usage): Adjust.
+ (m68k_elf_final_processing): Set CF EF flags.
+ * config/tc-m68k.h (m68k_init_after_args): Remove.
+ (tc_init_after_args): Remove.
+ * doc/c-m68k.texi (M68K-Opts): Document -march, -mcpu options.
+ (M68k-Directives): Document .arch and .cpu directives.
+
+2006-02-05 Arnold Metselaar <arnold.metselaar@planet.nl>
+
+ * config/tc-z80.c (z80_start_line_hook): allow .equ and .defl as
+ synonyms for equ and defl.
+ (z80_cons_fix_new): New function.
+ (emit_byte): Disallow relative jumps to absolute locations.
+ (emit_data): Only handle defb, prototype changed, because defb is
+ now handled as pseudo-op rather than an instruction.
+ (instab): Entries for defb,defw,db,dw moved from here...
+ (md_pseudo_table): ... to here, use generic cons() for defw,dw.
+ Add entries for def24,def32,d24,d32.
+ (md_assemble): Improved error handling.
+ (md_apply_fix): New case BFD_RELOC_24, set fixP->fx_no_overflow to one.
+ * config/tc-z80.h (TC_CONS_FIX_NEW): Define.
+ (z80_cons_fix_new): Declare.
+ * doc/c-z80.texi (defb, db): Mention warning on overflow.
+ (def24,d24,def32,d32): New pseudo-ops.
+
+2006-02-02 Paul Brook <paul@codesourcery.com>
+
+ * config/tc-arm.c (do_shift): Remove Thumb-1 constraint.
+
+2005-02-02 Paul Brook <paul@codesourcery.com>
+
+ * config/tc-arm.c (T2_OPCODE_MASK, T2_DATA_OP_SHIFT, T2_OPCODE_AND,
+ T2_OPCODE_BIC, T2_OPCODE_ORR, T2_OPCODE_ORN, T2_OPCODE_EOR,
+ T2_OPCODE_ADD, T2_OPCODE_ADC, T2_OPCODE_SBC, T2_OPCODE_SUB,
+ T2_OPCODE_RSB): Define.
+ (thumb32_negate_data_op): New function.
+ (md_apply_fix): Use it.
+
+2006-01-31 Bob Wilson <bob.wilson@acm.org>
+
+ * config/xtensa-istack.h (TInsn): Remove record_fix and sub_symbol
+ fields.
+ * config/tc-xtensa.h (xtensa_frag_type): Remove slot_sub_symbols field.
+ * config/tc-xtensa.c (md_apply_fix): Check for unexpected uses of
+ subtracted symbols.
+ (relaxation_requirements): Add pfinish_frag argument and use it to
+ replace setting tinsn->record_fix fields.
+ (xg_assemble_vliw_tokens): Adjust calls to relaxation_requirements
+ and vinsn_to_insnbuf. Remove references to record_fix and
+ slot_sub_symbols fields.
+ (xtensa_mark_narrow_branches): Delete unused code.
+ (is_narrow_branch_guaranteed_in_range): Handle expr that is not just
+ a symbol.
+ (convert_frag_immed): Adjust vinsn_to_insnbuf call and do not set
+ record_fix fields.
+ (tinsn_immed_from_frag): Remove code for handling slot_sub_symbols.
+ (vinsn_to_insnbuf): Change use of record_fixup argument, replacing use
+ of the record_fix field. Simplify error messages for unexpected
+ symbolic operands.
+ (set_expr_symbol_offset_diff): Delete.
+
+2006-01-31 Paul Brook <paul@codesourcery.com>
+
+ * config/tc-arm.c (arm_reg_parse): Check if reg is non-NULL.
+
+2006-01-31 Paul Brook <paul@codesourcery.com>
+ Richard Earnshaw <rearnsha@arm.com>
+
+ * config/tc-arm.c: Use arm_feature_set.
+ (arm_ext_*, arm_arch_full, arm_arch_t2, arm_arch_none,
+ arm_cext_iwmmxt, arm_cext_xscale, arm_cext_maverick, fpu_fpa_ext_v1,
+ fpu_fpa_ext_v2, fpu_vfp_ext_v1xd, fpu_vfp_ext_v1, fpu_vfp_ext_v2):
+ New variables.
+ (insns): Use them.
+ (md_atof, opcode_select, opcode_select, md_assemble, md_assemble,
+ md_begin, arm_parse_extension, arm_parse_cpu, arm_parse_arch,
+ arm_parse_fpu, arm_parse_float_abi, aeabi_set_public_attributes,
+ s_arm_cpu, s_arm_arch, s_arm_fpu): Use macros for accessing CPU
+ feature flags.
+ (arm_legacy_option_table, arm_option_cpu_value_table): New types.
+ (arm_opts): Move old cpu/arch options from here...
+ (arm_legacy_opts): ... to here.
+ (md_parse_option): Search arm_legacy_opts.
+ (arm_cpus, arm_archs, arm_extensions, arm_fpus)
+ (arm_float_abis, arm_eabis): Make const.
+
2006-01-25 Bob Wilson <bob.wilson@acm.org>
* config/tc-xtensa.c (md_apply_fix): Set value to zero for PLT relocs.
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