add dct hardware with device driver

[fpga-leon-mjpeg/leon-mjpeg.git] / grlib-gpl-1.0.22-b4095 / lib / kuri / mjpeg / mjpeg.vhd

diff --git a/grlib-gpl-1.0.22-b4095/lib/kuri/mjpeg/mjpeg.vhd b/grlib-gpl-1.0.22-b4095/lib/kuri/mjpeg/mjpeg.vhd
index a66dfdd..8d8b4e9 100644 (file)
--- a/grlib-gpl-1.0.22-b4095/lib/kuri/mjpeg/mjpeg.vhd
+++ b/grlib-gpl-1.0.22-b4095/lib/kuri/mjpeg/mjpeg.vhd
@@ -12,10 +12,95 @@ use techmap.gencomp.all;
 
 package mjpeg is
 
+component dctycc is
+   generic (
+      memtech : integer := DEFMEMTECH;
+--      fifo_depth : integer := 32;
+      shindex : integer := 0;
+      haddr  : integer := 0;
+      hmask  : integer := 16#fff#;
+      hirq   : integer := 0;      
+      pindex : integer := 0;
+      paddr  : integer := 0;
+      pmask  : integer := 16#fff#;
+      mhindex : integer := 0;
+      chprot : integer := 3);
+   port (
+      rst   : in std_ulogic;
+      clk   : in std_ulogic;
+      ahbmi : in ahb_mst_in_type;
+      ahbmo : out ahb_mst_out_type;
+      ahbsi : in ahb_slv_in_type;
+      ahbso : out ahb_slv_out_type;
+      apbi  : in apb_slv_in_type;
+      apbo  : out apb_slv_out_type
+   );
+end component;
+
+component dctmem1cont is
+   generic (
+      memtech : integer := DEFMEMTECH);
+   port (
+      rst   : in std_ulogic;
+      clk   : in std_ulogic;
+      kready1  : out std_logic;
+      kstrobe1 : in std_logic;
+      kdata1   : in std_logic_vector(11 downto 0);
+      kready2  : in std_logic;
+      kstrobe2 : out std_logic;
+      kdata2   : out std_logic_vector(11 downto 0);
+      error    : out std_logic;
+      samp_fact : in std_logic;
+      kstrobeq1 : in std_logic;
+      kdataq1   : in std_logic_vector(7 downto 0);
+      kdataq2   : out std_logic_vector(7 downto 0)
+   );
+end component;
+
+component dctmem2cont is
+   generic (
+      memtech : integer := DEFMEMTECH);
+   port (
+      rst   : in std_ulogic;
+      clk   : in std_ulogic;
+      kready1  : out std_logic;
+      kstrobe1 : in std_logic;
+      kdata1   : in std_logic_vector(15 downto 0);
+      kready2  : in std_logic;
+      kstrobe2 : out std_logic;
+      kdata2   : out std_logic_vector(15 downto 0);
+      error     : out std_logic
+   );
+end component;
+
+component idct1 is
+    port ( rst : in  std_ulogic;
+           clk : in  std_ulogic;
+           ready1 : out std_logic;
+           strobe1 : in std_logic;
+           coeffin : in  std_logic_vector (11 downto 0);
+           quantin : in  std_logic_vector (7 downto 0);
+           outdata : out  std_logic_vector (15 downto 0);
+           ready2 : in std_logic;
+           strobe2 : out std_logic
+           );
+end component;
+
+component idct2 is
+    port ( rst : in  std_ulogic;
+           clk : in  std_ulogic;
+           ready1 : out std_logic;
+           strobe1 : in std_logic;
+           coeffin : in  std_logic_vector (15 downto 0);
+           outdata : out  std_logic_vector (7 downto 0);
+           ready2 : in std_logic;
+           strobe2 : out std_logic
+           );
+end component;
+
 component upycc
   generic (
     memtech : integer := DEFMEMTECH;
---    fifo_depth : integer := 32;
     shindex : integer := 0;
     haddr  : integer := 0;
     hmask  : integer := 16#fff#;
@@ -56,16 +141,18 @@ component yccambaif
       apbo  : out apb_slv_out_type;
       kready : in std_logic;
       kstrobe : out std_logic;
-      kdata   : out std_logic_vector(7 downto 0);
+      kdata   : out std_logic_vector(11 downto 0);
       samp_fact : out std_logic;
-      error : in std_logic;
+      error : in std_logic_vector(2 downto 0);
       xmcumax : out std_logic_vector(5 downto 0);
       ymcumax : out std_logic_vector(4 downto 0);
       incaddy  : out std_logic_vector(15 downto 0);
       incaddmcux : out std_logic_vector(15 downto 0);
       incaddmcuy : out std_logic_vector(10 downto 0);
       fbstartadd : out std_logic_vector(31 downto 0);
-      startgen : out std_logic
+      startgen : out std_logic;
+      kstrobeq : out std_logic;
+      kdataq : out std_logic_vector(7 downto 0)
    );
 end component;