#include "qemu/osdep.h"
#include "qemu/datadir.h"
#include "qemu/memalign.h"
+#include "qemu/guest-random.h"
#include "qapi/error.h"
#include "qapi/qapi-events-machine.h"
#include "qapi/qapi-events-qdev.h"
#include "hw/ppc/fdt.h"
#include "hw/ppc/spapr.h"
+#include "hw/ppc/spapr_nested.h"
#include "hw/ppc/spapr_vio.h"
+#include "hw/ppc/vof.h"
#include "hw/qdev-properties.h"
#include "hw/pci-host/spapr.h"
#include "hw/pci/msi.h"
int smt_threads)
{
int i, ret = 0;
- uint32_t servers_prop[smt_threads];
- uint32_t gservers_prop[smt_threads * 2];
+ g_autofree uint32_t *servers_prop = g_new(uint32_t, smt_threads);
+ g_autofree uint32_t *gservers_prop = g_new(uint32_t, smt_threads * 2);
int index = spapr_get_vcpu_id(cpu);
if (cpu->compat_pvr) {
gservers_prop[i*2 + 1] = 0;
}
ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
- servers_prop, sizeof(servers_prop));
+ servers_prop, sizeof(*servers_prop) * smt_threads);
if (ret < 0) {
return ret;
}
ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s",
- gservers_prop, sizeof(gservers_prop));
+ gservers_prop, sizeof(*gservers_prop) * smt_threads * 2);
return ret;
}
{
MachineState *machine = MACHINE(spapr);
SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
+ uint8_t rng_seed[32];
int chosen;
_FDT(chosen = fdt_add_subnode(fdt, 0, "chosen"));
spapr_dt_ov5_platform_support(spapr, fdt, chosen);
}
+ qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed));
+ _FDT(fdt_setprop(fdt, chosen, "rng-seed", rng_seed, sizeof(rng_seed)));
+
_FDT(spapr_dt_ovec(fdt, chosen, spapr->ov5_cas, "ibm,architecture-vec-5"));
}
patb = spapr->nested_ptcr & PTCR_PATB;
pats = spapr->nested_ptcr & PTCR_PATS;
+ /* Check if partition table is properly aligned */
+ if (patb & MAKE_64BIT_MASK(0, pats + 12)) {
+ return false;
+ }
+
/* Calculate number of entries */
pats = 1ull << (pats + 12 - 4);
if (pats <= lpid) {
void spapr_free_hpt(SpaprMachineState *spapr)
{
- g_free(spapr->htab);
+ qemu_vfree(spapr->htab);
spapr->htab = NULL;
spapr->htab_shift = 0;
close_htab_fd(spapr);
}
}
-static void spapr_machine_reset(MachineState *machine)
+static void spapr_machine_reset(MachineState *machine, ShutdownCause reason)
{
SpaprMachineState *spapr = SPAPR_MACHINE(machine);
PowerPCCPU *first_ppc_cpu;
spapr_setup_hpt(spapr);
}
- qemu_devices_reset();
+ qemu_devices_reset(reason);
spapr_ovec_cleanup(spapr->ov5_cas);
spapr->ov5_cas = spapr_ovec_new();
spapr->fdt_initial_size = spapr->fdt_size;
spapr->fdt_blob = fdt;
+ /* Set machine->fdt for 'dumpdtb' QMP/HMP command */
+ machine->fdt = fdt;
+
/* Set up the entry state */
first_ppc_cpu->env.gpr[5] = 0;
break;
}
}
- } while ((index < htabslots) && !qemu_file_rate_limit(f));
+ } while ((index < htabslots) && !migration_rate_exceeded(f));
if (index >= htabslots) {
assert(index == htabslots);
assert(index == htabslots);
index = 0;
}
- } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final));
+ } while ((examined < htabslots) && (!migration_rate_exceeded(f) || final));
if (index >= htabslots) {
assert(index == htabslots);
int ret;
unsigned int smp_threads = ms->smp.threads;
- if (!kvm_enabled() && (smp_threads > 1)) {
+ if (tcg_enabled() && (smp_threads > 1)) {
error_setg(errp, "TCG cannot support more than 1 thread/core "
"on a pseries machine");
return;
qapi_event_send_mem_unplug_error(dev->id ? : "", qapi_error);
- qapi_event_send_device_unplug_guest_error(!!dev->id, dev->id,
+ qapi_event_send_device_unplug_guest_error(dev->id,
dev->canonical_path);
}
smc->dr_lmb_enabled = true;
smc->update_dt_enabled = true;
- mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0");
+ mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.2");
mc->has_hotpluggable_cpus = true;
mc->nvdimm_supported = true;
smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED;
smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_ON;
smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_ON;
smc->default_caps.caps[SPAPR_CAP_RPT_INVALIDATE] = SPAPR_CAP_OFF;
+
+ /*
+ * This cap specifies whether the AIL 3 mode for
+ * H_SET_RESOURCE is supported. The default is modified
+ * by default_caps_with_cpu().
+ */
+ smc->default_caps.caps[SPAPR_CAP_AIL_MODE_3] = SPAPR_CAP_ON;
spapr_caps_add_properties(smc);
smc->irq = &spapr_irq_dual;
smc->dr_phb_enabled = true;
type_init(spapr_machine_register_##suffix)
/*
+ * pseries-8.1
+ */
+static void spapr_machine_8_1_class_options(MachineClass *mc)
+{
+ /* Defaults for the latest behaviour inherited from the base class */
+}
+
+DEFINE_SPAPR_MACHINE(8_1, "8.1", true);
+
+/*
+ * pseries-8.0
+ */
+static void spapr_machine_8_0_class_options(MachineClass *mc)
+{
+ spapr_machine_8_1_class_options(mc);
+ compat_props_add(mc->compat_props, hw_compat_8_0, hw_compat_8_0_len);
+}
+
+DEFINE_SPAPR_MACHINE(8_0, "8.0", false);
+
+/*
+ * pseries-7.2
+ */
+static void spapr_machine_7_2_class_options(MachineClass *mc)
+{
+ spapr_machine_8_0_class_options(mc);
+ compat_props_add(mc->compat_props, hw_compat_7_2, hw_compat_7_2_len);
+}
+
+DEFINE_SPAPR_MACHINE(7_2, "7.2", false);
+
+/*
* pseries-7.1
*/
static void spapr_machine_7_1_class_options(MachineClass *mc)
{
- /* Defaults for the latest behaviour inherited from the base class */
+ spapr_machine_7_2_class_options(mc);
+ compat_props_add(mc->compat_props, hw_compat_7_1, hw_compat_7_1_len);
}
-DEFINE_SPAPR_MACHINE(7_1, "7.1", true);
+DEFINE_SPAPR_MACHINE(7_1, "7.1", false);
/*
* pseries-7.0
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