#include <stdio.h>
#include <string.h>
#include <sys/mman.h>
+#include <unistd.h>
#include <xf86drm.h>
#include "drv_priv.h"
#define I915_CACHELINE_SIZE 64
#define I915_CACHELINE_MASK (I915_CACHELINE_SIZE - 1)
-static const uint32_t render_target_formats[] = { DRM_FORMAT_ABGR8888, DRM_FORMAT_ARGB1555,
- DRM_FORMAT_ARGB8888, DRM_FORMAT_RGB565,
- DRM_FORMAT_XBGR2101010, DRM_FORMAT_XBGR8888,
- DRM_FORMAT_XRGB1555, DRM_FORMAT_XRGB2101010,
- DRM_FORMAT_XRGB8888 };
+static const uint32_t render_target_formats[] = { DRM_FORMAT_ABGR16161616F, DRM_FORMAT_ABGR2101010,
+ DRM_FORMAT_ABGR8888, DRM_FORMAT_ARGB2101010,
+ DRM_FORMAT_ARGB8888, DRM_FORMAT_RGB565,
+ DRM_FORMAT_XBGR2101010, DRM_FORMAT_XBGR8888,
+ DRM_FORMAT_XRGB2101010, DRM_FORMAT_XRGB8888 };
-static const uint32_t tileable_texture_source_formats[] = { DRM_FORMAT_GR88, DRM_FORMAT_R8,
- DRM_FORMAT_UYVY, DRM_FORMAT_YUYV };
-
-static const uint32_t texture_source_formats[] = { DRM_FORMAT_YVU420, DRM_FORMAT_YVU420_ANDROID,
- DRM_FORMAT_NV12 };
+static const uint32_t texture_source_formats[] = { DRM_FORMAT_R8, DRM_FORMAT_NV12, DRM_FORMAT_P010,
+ DRM_FORMAT_YVU420, DRM_FORMAT_YVU420_ANDROID };
struct i915_device {
uint32_t gen;
return combo->format == DRM_FORMAT_RGBA8888;
case DRM_FORMAT_BGRX8888:
return combo->format == DRM_FORMAT_BGRA8888;
+ case DRM_FORMAT_XRGB2101010:
+ return combo->format == DRM_FORMAT_ARGB2101010;
+ case DRM_FORMAT_XBGR2101010:
+ return combo->format == DRM_FORMAT_ABGR2101010;
default:
return false;
}
combo->use_flags |= item->use_flags & ~BO_USE_CURSOR;
}
+ /* If we can scanout NV12, we support all tiling modes. */
+ if (item->format == DRM_FORMAT_NV12)
+ combo->use_flags |= item->use_flags;
+
if (combo->metadata.modifier == item->modifier)
combo->use_flags |= item->use_flags;
}
drv_add_combinations(drv, texture_source_formats, ARRAY_SIZE(texture_source_formats),
&metadata, texture_use_flags);
- drv_add_combinations(drv, tileable_texture_source_formats,
- ARRAY_SIZE(tileable_texture_source_formats), &metadata,
- texture_use_flags);
+ /*
+ * Chrome uses DMA-buf mmap to write to YV12 buffers, which are then accessed by the
+ * Video Encoder Accelerator (VEA). It could also support NV12 potentially in the future.
+ */
+ drv_modify_combination(drv, DRM_FORMAT_YVU420, &metadata, BO_USE_HW_VIDEO_ENCODER);
+ drv_modify_combination(drv, DRM_FORMAT_NV12, &metadata,
+ BO_USE_HW_VIDEO_ENCODER | BO_USE_HW_VIDEO_DECODER);
+
+ /* Android CTS tests require this. */
+ drv_add_combination(drv, DRM_FORMAT_BGR888, &metadata, BO_USE_SW_MASK);
drv_modify_combination(drv, DRM_FORMAT_XRGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
drv_modify_combination(drv, DRM_FORMAT_ARGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
render_use_flags &= ~BO_USE_SW_WRITE_OFTEN;
render_use_flags &= ~BO_USE_SW_READ_OFTEN;
render_use_flags &= ~BO_USE_LINEAR;
+ render_use_flags &= ~BO_USE_PROTECTED;
texture_use_flags &= ~BO_USE_RENDERSCRIPT;
texture_use_flags &= ~BO_USE_SW_WRITE_OFTEN;
texture_use_flags &= ~BO_USE_SW_READ_OFTEN;
texture_use_flags &= ~BO_USE_LINEAR;
+ texture_use_flags &= ~BO_USE_PROTECTED;
metadata.tiling = I915_TILING_X;
metadata.priority = 2;
drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
&metadata, render_use_flags);
- drv_add_combinations(drv, tileable_texture_source_formats,
- ARRAY_SIZE(tileable_texture_source_formats), &metadata,
- texture_use_flags);
-
metadata.tiling = I915_TILING_Y;
metadata.priority = 3;
metadata.modifier = I915_FORMAT_MOD_Y_TILED;
drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
&metadata, render_use_flags);
- drv_add_combinations(drv, tileable_texture_source_formats,
- ARRAY_SIZE(tileable_texture_source_formats), &metadata,
- texture_use_flags);
+ /* Support y-tiled NV12 and P010 for libva */
+ drv_add_combination(drv, DRM_FORMAT_NV12, &metadata,
+ BO_USE_TEXTURE | BO_USE_HW_VIDEO_DECODER);
+ drv_add_combination(drv, DRM_FORMAT_P010, &metadata,
+ BO_USE_TEXTURE | BO_USE_HW_VIDEO_DECODER);
kms_items = drv_query_kms(drv);
if (!kms_items)
break;
}
- *aligned_height = ALIGN(bo->height, vertical_alignment);
+ *aligned_height = ALIGN(*aligned_height, vertical_alignment);
if (i915->gen > 3) {
*stride = ALIGN(*stride, horizontal_alignment);
} else {
{
uint32_t offset;
size_t plane;
- int ret;
+ int ret, pagesize;
offset = 0;
+ pagesize = getpagesize();
for (plane = 0; plane < drv_num_planes_from_format(format); plane++) {
uint32_t stride = drv_stride_from_format(format, width, plane);
uint32_t plane_height = drv_height_from_format(format, height, plane);
- if (bo->tiling != I915_TILING_NONE)
- assert(IS_ALIGNED(offset, 4096));
+ if (bo->meta.tiling != I915_TILING_NONE)
+ assert(IS_ALIGNED(offset, pagesize));
- ret = i915_align_dimensions(bo, bo->tiling, &stride, &plane_height);
+ ret = i915_align_dimensions(bo, bo->meta.tiling, &stride, &plane_height);
if (ret)
return ret;
- bo->strides[plane] = stride;
- bo->sizes[plane] = stride * plane_height;
- bo->offsets[plane] = offset;
- offset += bo->sizes[plane];
+ bo->meta.strides[plane] = stride;
+ bo->meta.sizes[plane] = stride * plane_height;
+ bo->meta.offsets[plane] = offset;
+ offset += bo->meta.sizes[plane];
}
- bo->total_size = offset;
+ bo->meta.total_size = ALIGN(offset, pagesize);
return 0;
}
switch (modifier) {
case DRM_FORMAT_MOD_LINEAR:
- bo->tiling = I915_TILING_NONE;
+ bo->meta.tiling = I915_TILING_NONE;
break;
case I915_FORMAT_MOD_X_TILED:
- bo->tiling = I915_TILING_X;
+ bo->meta.tiling = I915_TILING_X;
break;
case I915_FORMAT_MOD_Y_TILED:
- bo->tiling = I915_TILING_Y;
+ bo->meta.tiling = I915_TILING_Y;
break;
}
- bo->format_modifiers[0] = modifier;
+ bo->meta.format_modifiers[0] = modifier;
if (format == DRM_FORMAT_YVU420_ANDROID) {
/*
}
memset(&gem_create, 0, sizeof(gem_create));
- gem_create.size = bo->total_size;
+ gem_create.size = bo->meta.total_size;
ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_CREATE, &gem_create);
if (ret) {
drv_log("DRM_IOCTL_I915_GEM_CREATE failed (size=%llu)\n", gem_create.size);
- return ret;
+ return -errno;
}
- for (plane = 0; plane < bo->num_planes; plane++)
+ for (plane = 0; plane < bo->meta.num_planes; plane++)
bo->handles[plane].u32 = gem_create.handle;
memset(&gem_set_tiling, 0, sizeof(gem_set_tiling));
gem_set_tiling.handle = bo->handles[0].u32;
- gem_set_tiling.tiling_mode = bo->tiling;
- gem_set_tiling.stride = bo->strides[0];
+ gem_set_tiling.tiling_mode = bo->meta.tiling;
+ gem_set_tiling.stride = bo->meta.strides[0];
ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_SET_TILING, &gem_set_tiling);
if (ret) {
return ret;
}
- bo->tiling = gem_get_tiling.tiling_mode;
+ bo->meta.tiling = gem_get_tiling.tiling_mode;
return 0;
}
int ret;
void *addr;
- if (bo->tiling == I915_TILING_NONE) {
+ if (bo->meta.tiling == I915_TILING_NONE) {
struct drm_i915_gem_mmap gem_map;
memset(&gem_map, 0, sizeof(gem_map));
- if ((bo->use_flags & BO_USE_SCANOUT) && !(bo->use_flags & BO_USE_RENDERSCRIPT))
+ /* TODO(b/118799155): We don't seem to have a good way to
+ * detect the use cases for which WC mapping is really needed.
+ * The current heuristic seems overly coarse and may be slowing
+ * down some other use cases unnecessarily.
+ *
+ * For now, care must be taken not to use WC mappings for
+ * Renderscript and camera use cases, as they're
+ * performance-sensitive. */
+ if ((bo->meta.use_flags & BO_USE_SCANOUT) &&
+ !(bo->meta.use_flags &
+ (BO_USE_RENDERSCRIPT | BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE)))
gem_map.flags = I915_MMAP_WC;
gem_map.handle = bo->handles[0].u32;
gem_map.offset = 0;
- gem_map.size = bo->total_size;
+ gem_map.size = bo->meta.total_size;
ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_MMAP, &gem_map);
if (ret) {
return MAP_FAILED;
}
- addr = mmap(0, bo->total_size, drv_get_prot(map_flags), MAP_SHARED, bo->drv->fd,
- gem_map.offset);
+ addr = mmap(0, bo->meta.total_size, drv_get_prot(map_flags), MAP_SHARED,
+ bo->drv->fd, gem_map.offset);
}
if (addr == MAP_FAILED) {
return addr;
}
- vma->length = bo->total_size;
+ vma->length = bo->meta.total_size;
return addr;
}
memset(&set_domain, 0, sizeof(set_domain));
set_domain.handle = bo->handles[0].u32;
- if (bo->tiling == I915_TILING_NONE) {
+ if (bo->meta.tiling == I915_TILING_NONE) {
set_domain.read_domains = I915_GEM_DOMAIN_CPU;
if (mapping->vma->map_flags & BO_MAP_WRITE)
set_domain.write_domain = I915_GEM_DOMAIN_CPU;
static int i915_bo_flush(struct bo *bo, struct mapping *mapping)
{
struct i915_device *i915 = bo->drv->priv;
- if (!i915->has_llc && bo->tiling == I915_TILING_NONE)
+ if (!i915->has_llc && bo->meta.tiling == I915_TILING_NONE)
i915_clflush(mapping->vma->addr, mapping->vma->length);
return 0;
}
-static uint32_t i915_resolve_format(uint32_t format, uint64_t use_flags)
+static uint32_t i915_resolve_format(struct driver *drv, uint32_t format, uint64_t use_flags)
{
switch (format) {
case DRM_FORMAT_FLEX_IMPLEMENTATION_DEFINED:
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