Merge tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dledford/rdma

[android-x86/kernel.git] / include / linux / mlx5 / device.h

diff --git a/include/linux/mlx5/device.h b/include/linux/mlx5/device.h
index b7eaccf..987764a 100644 (file)
--- a/include/linux/mlx5/device.h
+++ b/include/linux/mlx5/device.h
@@ -259,6 +259,7 @@ enum mlx5_event {
        MLX5_EVENT_TYPE_PAGE_REQUEST       = 0xb,
 
        MLX5_EVENT_TYPE_PAGE_FAULT         = 0xc,
+       MLX5_EVENT_TYPE_NIC_VPORT_CHANGE   = 0xd,
 };
 
 enum {
@@ -553,6 +554,12 @@ struct mlx5_eqe_page_fault {
        __be32 flags_qpn;
 } __packed;
 
+struct mlx5_eqe_vport_change {
+       u8              rsvd0[2];
+       __be16          vport_num;
+       __be32          rsvd1[6];
+} __packed;
+
 union ev_data {
        __be32                          raw[7];
        struct mlx5_eqe_cmd             cmd;
@@ -565,6 +572,7 @@ union ev_data {
        struct mlx5_eqe_stall_vl        stall_vl;
        struct mlx5_eqe_page_req        req_pages;
        struct mlx5_eqe_page_fault      page_fault;
+       struct mlx5_eqe_vport_change    vport_change;
 } __packed;
 
 struct mlx5_eqe {
@@ -626,7 +634,8 @@ struct mlx5_cqe64 {
        __be32          imm_inval_pkey;
        u8              rsvd40[4];
        __be32          byte_cnt;
-       __be64          timestamp;
+       __be32          timestamp_h;
+       __be32          timestamp_l;
        __be32          sop_drop_qpn;
        __be16          wqe_counter;
        u8              signature;
@@ -648,6 +657,16 @@ static inline int cqe_has_vlan(struct mlx5_cqe64 *cqe)
        return !!(cqe->l4_hdr_type_etc & 0x1);
 }
 
+static inline u64 get_cqe_ts(struct mlx5_cqe64 *cqe)
+{
+       u32 hi, lo;
+
+       hi = be32_to_cpu(cqe->timestamp_h);
+       lo = be32_to_cpu(cqe->timestamp_l);
+
+       return (u64)lo | ((u64)hi << 32);
+}
+
 enum {
        CQE_L4_HDR_TYPE_NONE                    = 0x0,
        CQE_L4_HDR_TYPE_TCP_NO_ACK              = 0x1,
@@ -1106,6 +1125,12 @@ enum {
 };
 
 enum {
+       MLX5_ESW_VPORT_ADMIN_STATE_DOWN  = 0x0,
+       MLX5_ESW_VPORT_ADMIN_STATE_UP    = 0x1,
+       MLX5_ESW_VPORT_ADMIN_STATE_AUTO  = 0x2,
+};
+
+enum {
        MLX5_L3_PROT_TYPE_IPV4          = 0,
        MLX5_L3_PROT_TYPE_IPV6          = 1,
 };
@@ -1141,6 +1166,12 @@ enum {
        MLX5_FLOW_CONTEXT_DEST_TYPE_TIR         = 2,
 };
 
+enum mlx5_list_type {
+       MLX5_NVPRT_LIST_TYPE_UC   = 0x0,
+       MLX5_NVPRT_LIST_TYPE_MC   = 0x1,
+       MLX5_NVPRT_LIST_TYPE_VLAN = 0x2,
+};
+
 enum {
        MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
        MLX5_RQC_RQ_TYPE_MEMORY_RQ_RPM    = 0x1,
@@ -1163,6 +1194,8 @@ enum mlx5_cap_type {
        MLX5_CAP_IPOIB_OFFLOADS,
        MLX5_CAP_EOIB_OFFLOADS,
        MLX5_CAP_FLOW_TABLE,
+       MLX5_CAP_ESWITCH_FLOW_TABLE,
+       MLX5_CAP_ESWITCH,
        /* NUM OF CAP Types */
        MLX5_CAP_NUM
 };
@@ -1200,6 +1233,28 @@ enum mlx5_cap_type {
 #define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \
        MLX5_GET(flow_table_nic_cap, mdev->hca_caps_max[MLX5_CAP_FLOW_TABLE], cap)
 
+#define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \
+       MLX5_GET(flow_table_eswitch_cap, \
+                mdev->hca_caps_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
+
+#define MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, cap) \
+       MLX5_GET(flow_table_eswitch_cap, \
+                mdev->hca_caps_max[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
+
+#define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \
+       MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap)
+
+#define MLX5_CAP_ESW_FLOWTABLE_FDB_MAX(mdev, cap) \
+       MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_nic_esw_fdb.cap)
+
+#define MLX5_CAP_ESW(mdev, cap) \
+       MLX5_GET(e_switch_cap, \
+                mdev->hca_caps_cur[MLX5_CAP_ESWITCH], cap)
+
+#define MLX5_CAP_ESW_MAX(mdev, cap) \
+       MLX5_GET(e_switch_cap, \
+                mdev->hca_caps_max[MLX5_CAP_ESWITCH], cap)
+
 #define MLX5_CAP_ODP(mdev, cap)\
        MLX5_GET(odp_cap, mdev->hca_caps_cur[MLX5_CAP_ODP], cap)
 
@@ -1239,4 +1294,6 @@ static inline u16 mlx5_to_sw_pkey_sz(int pkey_sz)
        return MLX5_MIN_PKEY_TABLE_SIZE << pkey_sz;
 }
 
+#define MLX5_BY_PASS_NUM_PRIOS 9
+
 #endif /* MLX5_DEVICE_H */