-//===-- llvm/CodeGen/LiveRegUnits.h - Live register unit set ----*- C++ -*-===//
+//===- llvm/CodeGen/LiveRegUnits.h - Register Unit Set ----------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
//
//===----------------------------------------------------------------------===//
//
-// This file implements a Set of live register units. This can be used for ad
-// hoc liveness tracking after register allocation. You can start with the
-// live-ins/live-outs at the beginning/end of a block and update the information
-// while walking the instructions inside the block.
+/// \file
+/// A set of register units. It is intended for register liveness tracking.
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_CODEGEN_LIVEREGUNITS_H
#define LLVM_CODEGEN_LIVEREGUNITS_H
-#include "llvm/ADT/SparseSet.h"
-#include "llvm/CodeGen/MachineBasicBlock.h"
+#include "llvm/ADT/BitVector.h"
+#include "llvm/MC/LaneBitmask.h"
+#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/Target/TargetRegisterInfo.h"
-#include <cassert>
+#include <cstdint>
namespace llvm {
class MachineInstr;
+class MachineBasicBlock;
-/// A set of live register units with functions to track liveness when walking
-/// backward/forward through a basic block.
+/// A set of register units used to track register liveness.
class LiveRegUnits {
- SparseSet<unsigned> LiveUnits;
+ const TargetRegisterInfo *TRI = nullptr;
+ BitVector Units;
- LiveRegUnits(const LiveRegUnits&) LLVM_DELETED_FUNCTION;
- LiveRegUnits &operator=(const LiveRegUnits&) LLVM_DELETED_FUNCTION;
public:
- /// \brief Constructs a new empty LiveRegUnits set.
- LiveRegUnits() {}
+ /// Constructs a new empty LiveRegUnits set.
+ LiveRegUnits() = default;
- void init(const TargetRegisterInfo *TRI) {
- LiveUnits.clear();
- LiveUnits.setUniverse(TRI->getNumRegs());
+ /// Constructs and initialize an empty LiveRegUnits set.
+ LiveRegUnits(const TargetRegisterInfo &TRI) {
+ init(TRI);
}
- void clear() { LiveUnits.clear(); }
+ /// Initialize and clear the set.
+ void init(const TargetRegisterInfo &TRI) {
+ this->TRI = &TRI;
+ Units.reset();
+ Units.resize(TRI.getNumRegUnits());
+ }
+
+ /// Clears the set.
+ void clear() { Units.reset(); }
+
+ /// Returns true if the set is empty.
+ bool empty() const { return Units.empty(); }
- bool empty() const { return LiveUnits.empty(); }
+ /// Adds register units covered by physical register \p Reg.
+ void addReg(unsigned Reg) {
+ for (MCRegUnitIterator Unit(Reg, TRI); Unit.isValid(); ++Unit)
+ Units.set(*Unit);
+ }
- /// \brief Adds a register to the set.
- void addReg(unsigned Reg, const MCRegisterInfo &MCRI) {
- for (MCRegUnitIterator RUnits(Reg, &MCRI); RUnits.isValid(); ++RUnits)
- LiveUnits.insert(*RUnits);
+ /// \brief Adds register units covered by physical register \p Reg that are
+ /// part of the lanemask \p Mask.
+ void addRegMasked(unsigned Reg, LaneBitmask Mask) {
+ for (MCRegUnitMaskIterator Unit(Reg, TRI); Unit.isValid(); ++Unit) {
+ LaneBitmask UnitMask = (*Unit).second;
+ if (UnitMask.none() || (UnitMask & Mask).any())
+ Units.set((*Unit).first);
+ }
}
- /// \brief Removes a register from the set.
- void removeReg(unsigned Reg, const MCRegisterInfo &MCRI) {
- for (MCRegUnitIterator RUnits(Reg, &MCRI); RUnits.isValid(); ++RUnits)
- LiveUnits.erase(*RUnits);
+ /// Removes all register units covered by physical register \p Reg.
+ void removeReg(unsigned Reg) {
+ for (MCRegUnitIterator Unit(Reg, TRI); Unit.isValid(); ++Unit)
+ Units.reset(*Unit);
}
- /// \brief Removes registers clobbered by the regmask operand @p Op.
- void removeRegsInMask(const MachineOperand &Op, const MCRegisterInfo &MCRI);
+ /// Removes register units not preserved by the regmask \p RegMask.
+ /// The regmask has the same format as the one in the RegMask machine operand.
+ void removeRegsNotPreserved(const uint32_t *RegMask);
+
+ /// Adds register units not preserved by the regmask \p RegMask.
+ /// The regmask has the same format as the one in the RegMask machine operand.
+ void addRegsInMask(const uint32_t *RegMask);
- /// \brief Returns true if register @p Reg (or one of its super register) is
- /// contained in the set.
- bool contains(unsigned Reg, const MCRegisterInfo &MCRI) const {
- for (MCRegUnitIterator RUnits(Reg, &MCRI); RUnits.isValid(); ++RUnits) {
- if (LiveUnits.count(*RUnits))
- return true;
+ /// Returns true if no part of physical register \p Reg is live.
+ bool available(unsigned Reg) const {
+ for (MCRegUnitIterator Unit(Reg, TRI); Unit.isValid(); ++Unit) {
+ if (Units.test(*Unit))
+ return false;
}
- return false;
+ return true;
}
- /// \brief Simulates liveness when stepping backwards over an
- /// instruction(bundle): Remove Defs, add uses.
- void stepBackward(const MachineInstr &MI, const MCRegisterInfo &MCRI);
+ /// Updates liveness when stepping backwards over the instruction \p MI.
+ void stepBackward(const MachineInstr &MI);
- /// \brief Simulates liveness when stepping forward over an
- /// instruction(bundle): Remove killed-uses, add defs.
- void stepForward(const MachineInstr &MI, const MCRegisterInfo &MCRI);
+ /// Mark all register units live during instruction \p MI.
+ /// This can be used to accumulate live/unoccupied registers over a range of
+ /// instructions.
+ void accumulateBackward(const MachineInstr &MI);
- /// \brief Adds all registers in the live-in list of block @p BB.
- void addLiveIns(const MachineBasicBlock *MBB, const MCRegisterInfo &MCRI);
+ /// Adds registers living out of block \p MBB.
+ /// Live out registers are the union of the live-in registers of the successor
+ /// blocks and pristine registers. Live out registers of the end block are the
+ /// callee saved registers.
+ void addLiveOuts(const MachineBasicBlock &MBB);
+
+ /// Adds registers living into block \p MBB.
+ void addLiveIns(const MachineBasicBlock &MBB);
+
+ /// Adds all register units marked in the bitvector \p RegUnits.
+ void addUnits(const BitVector &RegUnits) {
+ Units |= RegUnits;
+ }
+ /// Removes all register units marked in the bitvector \p RegUnits.
+ void removeUnits(const BitVector &RegUnits) {
+ Units.reset(RegUnits);
+ }
+ /// Return the internal bitvector representation of the set.
+ const BitVector &getBitVector() const {
+ return Units;
+ }
};
-} // namespace llvm
+} // end namespace llvm
-#endif
+#endif // LLVM_CODEGEN_LIVEREGUNITS_H
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