modetest: get the crtc_id from the pipe_arg

[android-x86/external-libdrm.git] / intel / intel_bufmgr.c

diff --git a/intel/intel_bufmgr.c b/intel/intel_bufmgr.c
index bede0a2..68d97c0 100644 (file)
--- a/intel/intel_bufmgr.c
+++ b/intel/intel_bufmgr.c
@@ -32,7 +32,9 @@
 #include <errno.h>
 #include <drm.h>
 #include <i915_drm.h>
+#ifndef __ANDROID__
 #include <pciaccess.h>
+#endif
 #include "libdrm_macros.h"
 #include "intel_bufmgr.h"
 #include "intel_bufmgr_priv.h"
@@ -43,21 +45,21 @@
  * Convenience functions for buffer management methods.
  */
 
-drm_intel_bo *
+drm_public drm_intel_bo *
 drm_intel_bo_alloc(drm_intel_bufmgr *bufmgr, const char *name,
                   unsigned long size, unsigned int alignment)
 {
        return bufmgr->bo_alloc(bufmgr, name, size, alignment);
 }
 
-drm_intel_bo *
+drm_public drm_intel_bo *
 drm_intel_bo_alloc_for_render(drm_intel_bufmgr *bufmgr, const char *name,
                              unsigned long size, unsigned int alignment)
 {
        return bufmgr->bo_alloc_for_render(bufmgr, name, size, alignment);
 }
 
-drm_intel_bo *
+drm_public drm_intel_bo *
 drm_intel_bo_alloc_userptr(drm_intel_bufmgr *bufmgr,
                           const char *name, void *addr,
                           uint32_t tiling_mode,
@@ -71,7 +73,7 @@ drm_intel_bo_alloc_userptr(drm_intel_bufmgr *bufmgr,
        return NULL;
 }
 
-drm_intel_bo *
+drm_public drm_intel_bo *
 drm_intel_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name,
                         int x, int y, int cpp, uint32_t *tiling_mode,
                         unsigned long *pitch, unsigned long flags)
@@ -80,13 +82,13 @@ drm_intel_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name,
                                      tiling_mode, pitch, flags);
 }
 
-void
+drm_public void
 drm_intel_bo_reference(drm_intel_bo *bo)
 {
        bo->bufmgr->bo_reference(bo);
 }
 
-void
+drm_public void
 drm_intel_bo_unreference(drm_intel_bo *bo)
 {
        if (bo == NULL)
@@ -95,26 +97,26 @@ drm_intel_bo_unreference(drm_intel_bo *bo)
        bo->bufmgr->bo_unreference(bo);
 }
 
-int
+drm_public int
 drm_intel_bo_map(drm_intel_bo *buf, int write_enable)
 {
        return buf->bufmgr->bo_map(buf, write_enable);
 }
 
-int
+drm_public int
 drm_intel_bo_unmap(drm_intel_bo *buf)
 {
        return buf->bufmgr->bo_unmap(buf);
 }
 
-int
+drm_public int
 drm_intel_bo_subdata(drm_intel_bo *bo, unsigned long offset,
                     unsigned long size, const void *data)
 {
        return bo->bufmgr->bo_subdata(bo, offset, size, data);
 }
 
-int
+drm_public int
 drm_intel_bo_get_subdata(drm_intel_bo *bo, unsigned long offset,
                         unsigned long size, void *data)
 {
@@ -133,26 +135,26 @@ drm_intel_bo_get_subdata(drm_intel_bo *bo, unsigned long offset,
        return 0;
 }
 
-void
+drm_public void
 drm_intel_bo_wait_rendering(drm_intel_bo *bo)
 {
        bo->bufmgr->bo_wait_rendering(bo);
 }
 
-void
+drm_public void
 drm_intel_bufmgr_destroy(drm_intel_bufmgr *bufmgr)
 {
        bufmgr->destroy(bufmgr);
 }
 
-int
+drm_public int
 drm_intel_bo_exec(drm_intel_bo *bo, int used,
                  drm_clip_rect_t * cliprects, int num_cliprects, int DR4)
 {
        return bo->bufmgr->bo_exec(bo, used, cliprects, num_cliprects, DR4);
 }
 
-int
+drm_public int
 drm_intel_bo_mrb_exec(drm_intel_bo *bo, int used,
                drm_clip_rect_t *cliprects, int num_cliprects, int DR4,
                unsigned int rings)
@@ -172,19 +174,19 @@ drm_intel_bo_mrb_exec(drm_intel_bo *bo, int used,
        }
 }
 
-void
+drm_public void
 drm_intel_bufmgr_set_debug(drm_intel_bufmgr *bufmgr, int enable_debug)
 {
        bufmgr->debug = enable_debug;
 }
 
-int
+drm_public int
 drm_intel_bufmgr_check_aperture_space(drm_intel_bo ** bo_array, int count)
 {
        return bo_array[0]->bufmgr->check_aperture_space(bo_array, count);
 }
 
-int
+drm_public int
 drm_intel_bo_flink(drm_intel_bo *bo, uint32_t * name)
 {
        if (bo->bufmgr->bo_flink)
@@ -193,7 +195,7 @@ drm_intel_bo_flink(drm_intel_bo *bo, uint32_t * name)
        return -ENODEV;
 }
 
-int
+drm_public int
 drm_intel_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
                        drm_intel_bo *target_bo, uint32_t target_offset,
                        uint32_t read_domains, uint32_t write_domain)
@@ -204,7 +206,7 @@ drm_intel_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
 }
 
 /* For fence registers, not GL fences */
-int
+drm_public int
 drm_intel_bo_emit_reloc_fence(drm_intel_bo *bo, uint32_t offset,
                              drm_intel_bo *target_bo, uint32_t target_offset,
                              uint32_t read_domains, uint32_t write_domain)
@@ -215,7 +217,7 @@ drm_intel_bo_emit_reloc_fence(drm_intel_bo *bo, uint32_t offset,
 }
 
 
-int
+drm_public int
 drm_intel_bo_pin(drm_intel_bo *bo, uint32_t alignment)
 {
        if (bo->bufmgr->bo_pin)
@@ -224,7 +226,7 @@ drm_intel_bo_pin(drm_intel_bo *bo, uint32_t alignment)
        return -ENODEV;
 }
 
-int
+drm_public int
 drm_intel_bo_unpin(drm_intel_bo *bo)
 {
        if (bo->bufmgr->bo_unpin)
@@ -233,7 +235,7 @@ drm_intel_bo_unpin(drm_intel_bo *bo)
        return -ENODEV;
 }
 
-int
+drm_public int
 drm_intel_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
                        uint32_t stride)
 {
@@ -244,7 +246,7 @@ drm_intel_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
        return 0;
 }
 
-int
+drm_public int
 drm_intel_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
                        uint32_t * swizzle_mode)
 {
@@ -256,7 +258,7 @@ drm_intel_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
        return 0;
 }
 
-int
+drm_public int
 drm_intel_bo_set_softpin_offset(drm_intel_bo *bo, uint64_t offset)
 {
        if (bo->bufmgr->bo_set_softpin_offset)
@@ -265,7 +267,7 @@ drm_intel_bo_set_softpin_offset(drm_intel_bo *bo, uint64_t offset)
        return -ENODEV;
 }
 
-int
+drm_public int
 drm_intel_bo_disable_reuse(drm_intel_bo *bo)
 {
        if (bo->bufmgr->bo_disable_reuse)
@@ -273,7 +275,7 @@ drm_intel_bo_disable_reuse(drm_intel_bo *bo)
        return 0;
 }
 
-int
+drm_public int
 drm_intel_bo_is_reusable(drm_intel_bo *bo)
 {
        if (bo->bufmgr->bo_is_reusable)
@@ -281,7 +283,7 @@ drm_intel_bo_is_reusable(drm_intel_bo *bo)
        return 0;
 }
 
-int
+drm_public int
 drm_intel_bo_busy(drm_intel_bo *bo)
 {
        if (bo->bufmgr->bo_busy)
@@ -289,7 +291,7 @@ drm_intel_bo_busy(drm_intel_bo *bo)
        return 0;
 }
 
-int
+drm_public int
 drm_intel_bo_madvise(drm_intel_bo *bo, int madv)
 {
        if (bo->bufmgr->bo_madvise)
@@ -297,7 +299,7 @@ drm_intel_bo_madvise(drm_intel_bo *bo, int madv)
        return -1;
 }
 
-int
+drm_public int
 drm_intel_bo_use_48b_address_range(drm_intel_bo *bo, uint32_t enable)
 {
        if (bo->bufmgr->bo_use_48b_address_range) {
@@ -308,13 +310,13 @@ drm_intel_bo_use_48b_address_range(drm_intel_bo *bo, uint32_t enable)
        return -ENODEV;
 }
 
-int
+drm_public int
 drm_intel_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
 {
        return bo->bufmgr->bo_references(bo, target_bo);
 }
 
-int
+drm_public int
 drm_intel_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, int crtc_id)
 {
        if (bufmgr->get_pipe_from_crtc_id)
@@ -322,6 +324,7 @@ drm_intel_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, int crtc_id)
        return -1;
 }
 
+#ifndef __ANDROID__
 static size_t
 drm_intel_probe_agp_aperture_size(int fd)
 {
@@ -347,8 +350,17 @@ err:
        pci_system_cleanup ();
        return size;
 }
+#else
+static size_t
+drm_intel_probe_agp_aperture_size(int fd)
+{
+       /* Nothing seems to rely on this value on Android anyway... */
+       fprintf(stderr, "%s: Mappable aperture size hardcoded to 64MiB\n", __func__);
+       return 64 * 1024 * 1024;
+}
+#endif
 
-int
+drm_public int
 drm_intel_get_aperture_sizes(int fd, size_t *mappable, size_t *total)
 {