break;
}
case AMDGPU::RETURN: {
- // RETURN instructions must have the live-out registers as implicit uses,
- // otherwise they appear dead.
- R600MachineFunctionInfo *MFI = MF->getInfo<R600MachineFunctionInfo>();
- MachineInstrBuilder MIB(*MF, MI);
- for (unsigned i = 0, e = MFI->LiveOuts.size(); i != e; ++i)
- MIB.addReg(MFI->LiveOuts[i], RegState::Implicit);
return BB;
}
}
switch(IntrinsicID) {
default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
case AMDGPUIntrinsic::r600_tex:
- case AMDGPUIntrinsic::r600_texc:
- case AMDGPUIntrinsic::r600_txl:
- case AMDGPUIntrinsic::r600_txlc:
- case AMDGPUIntrinsic::r600_txb:
- case AMDGPUIntrinsic::r600_txbc:
- case AMDGPUIntrinsic::r600_txf:
- case AMDGPUIntrinsic::r600_txq:
- case AMDGPUIntrinsic::r600_ddx:
- case AMDGPUIntrinsic::r600_ddy: {
+ case AMDGPUIntrinsic::r600_texc: {
unsigned TextureOp;
switch (IntrinsicID) {
case AMDGPUIntrinsic::r600_tex:
case AMDGPUIntrinsic::r600_texc:
TextureOp = 1;
break;
- case AMDGPUIntrinsic::r600_txl:
- TextureOp = 2;
- break;
- case AMDGPUIntrinsic::r600_txlc:
- TextureOp = 3;
- break;
- case AMDGPUIntrinsic::r600_txb:
- TextureOp = 4;
- break;
- case AMDGPUIntrinsic::r600_txbc:
- TextureOp = 5;
- break;
- case AMDGPUIntrinsic::r600_txf:
- TextureOp = 6;
- break;
- case AMDGPUIntrinsic::r600_txq:
- TextureOp = 7;
- break;
- case AMDGPUIntrinsic::r600_ddx:
- TextureOp = 8;
- break;
- case AMDGPUIntrinsic::r600_ddy:
- TextureOp = 9;
- break;
default:
llvm_unreachable("Unknow Texture Operation");
}