ARMInstructionSelector(const ARMBaseTargetMachine &TM, const ARMSubtarget &STI,
const ARMRegisterBankInfo &RBI);
- bool select(MachineInstr &I) const override;
+ bool select(MachineInstr &I, CodeGenCoverage &CoverageInfo) const override;
static const char *getName() { return DEBUG_TYPE; }
private:
- bool selectImpl(MachineInstr &I) const;
+ bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
struct CmpConstants;
struct InsertInfo;
return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
}
-bool ARMInstructionSelector::select(MachineInstr &I) const {
+bool ARMInstructionSelector::select(MachineInstr &I,
+ CodeGenCoverage &CoverageInfo) const {
assert(I.getParent() && "Instruction should be in a basic block!");
assert(I.getParent()->getParent() && "Instruction should be in a function!");
return true;
}
- if (selectImpl(I))
+ if (selectImpl(I, CoverageInfo))
return true;
MachineInstrBuilder MIB{MF, I};
I.setDesc(TII.get(ARM::ADDri));
MIB.addImm(0).add(predOps(ARMCC::AL)).add(condCodeOp());
break;
- case G_CONSTANT: {
- unsigned Reg = I.getOperand(0).getReg();
-
- if (!validReg(MRI, Reg, 32, ARM::GPRRegBankID))
- return false;
-
- I.setDesc(TII.get(ARM::MOVi));
- MIB.add(predOps(ARMCC::AL)).add(condCodeOp());
-
- auto &Val = I.getOperand(1);
- if (Val.isCImm()) {
- if (Val.getCImm()->getBitWidth() > 32)
- return false;
- Val.ChangeToImmediate(Val.getCImm()->getZExtValue());
- }
-
- if (!Val.isImm()) {
- return false;
- }
-
- break;
- }
case G_GLOBAL_VALUE:
return selectGlobal(MIB, MRI);
case G_STORE: