using namespace llvm;
+#define DEBUG_TYPE "amdgpu-subtarget"
+
#define GET_SUBTARGETINFO_ENUM
#define GET_SUBTARGETINFO_TARGET_DESC
#define GET_SUBTARGETINFO_CTOR
AMDGPUGenSubtargetInfo(TT, CPU, FS), DumpCode(false) {
InstrItins = getInstrItineraryForCPU(CPU);
- memset(CapsOverride, 0, sizeof(*CapsOverride)
- * AMDGPUDeviceInfo::MaxNumberCapabilities);
// Default card
StringRef GPU = CPU;
Is64bit = false;
- DefaultSize[0] = 64;
- DefaultSize[1] = 1;
- DefaultSize[2] = 1;
HasVertexCache = false;
+ TexVTXClauseSize = 0;
+ Gen = AMDGPUSubtarget::R600;
+ FP64 = false;
+ CaymanISA = false;
+ EnableIRStructurizer = true;
+ EnableIfCvt = true;
+ WavefrontSize = 0;
+ CFALUBug = false;
ParseSubtargetFeatures(GPU, FS);
DevName = GPU;
- Device = AMDGPUDeviceInfo::getDeviceFromName(DevName, this, Is64bit);
-}
-
-AMDGPUSubtarget::~AMDGPUSubtarget() {
- delete Device;
}
bool
-AMDGPUSubtarget::isOverride(AMDGPUDeviceInfo::Caps caps) const {
- assert(caps < AMDGPUDeviceInfo::MaxNumberCapabilities &&
- "Caps index is out of bounds!");
- return CapsOverride[caps];
-}
-bool
AMDGPUSubtarget::is64bit() const {
return Is64bit;
}
AMDGPUSubtarget::hasVertexCache() const {
return HasVertexCache;
}
+short
+AMDGPUSubtarget::getTexVTXClauseSize() const {
+ return TexVTXClauseSize;
+}
+enum AMDGPUSubtarget::Generation
+AMDGPUSubtarget::getGeneration() const {
+ return Gen;
+}
bool
-AMDGPUSubtarget::isTargetELF() const {
- return false;
+AMDGPUSubtarget::hasHWFP64() const {
+ return FP64;
+}
+bool
+AMDGPUSubtarget::hasCaymanISA() const {
+ return CaymanISA;
+}
+bool
+AMDGPUSubtarget::IsIRStructurizerEnabled() const {
+ return EnableIRStructurizer;
+}
+bool
+AMDGPUSubtarget::isIfCvtEnabled() const {
+ return EnableIfCvt;
}
-size_t
-AMDGPUSubtarget::getDefaultSize(uint32_t dim) const {
- if (dim > 3) {
- return 1;
- } else {
- return DefaultSize[dim];
+unsigned
+AMDGPUSubtarget::getWavefrontSize() const {
+ return WavefrontSize;
+}
+unsigned
+AMDGPUSubtarget::getStackEntrySize() const {
+ assert(getGeneration() <= NORTHERN_ISLANDS);
+ switch(getWavefrontSize()) {
+ case 16:
+ return 8;
+ case 32:
+ if (hasCaymanISA())
+ return 4;
+ else
+ return 8;
+ case 64:
+ return 4;
+ default:
+ llvm_unreachable("Illegal wavefront size.");
}
}
-
-std::string
-AMDGPUSubtarget::getDataLayout() const {
- if (!Device) {
- return std::string("e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16"
- "-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f80:32:32"
- "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64"
- "-v96:128:128-v128:128:128-v192:256:256-v256:256:256"
- "-v512:512:512-v1024:1024:1024-v2048:2048:2048-a0:0:64");
- }
- return Device->getDataLayout();
+bool
+AMDGPUSubtarget::hasCFAluBug() const {
+ assert(getGeneration() <= NORTHERN_ISLANDS);
+ return CFALUBug;
+}
+bool
+AMDGPUSubtarget::isTargetELF() const {
+ return false;
}
std::string
AMDGPUSubtarget::getDeviceName() const {
return DevName;
}
-const AMDGPUDevice *
-AMDGPUSubtarget::device() const {
- return Device;
-}