uip_arpをNYLPC_CIPV4ARPへ分離

[mimic/MiMicSDK.git] / lib / src / driver / uip / EtherDev_DP83848C_protected.h

diff --git a/lib/src/driver/uip/EtherDev_DP83848C_protected.h b/lib/src/driver/uip/EtherDev_DP83848C_protected.h
index c1c8dcb..e5757a0 100644 (file)
--- a/lib/src/driver/uip/EtherDev_DP83848C_protected.h
+++ b/lib/src/driver/uip/EtherDev_DP83848C_protected.h
@@ -12,40 +12,6 @@
 extern "C" {\r
 #endif /* __cplusplus */\r
 \r
-#define DP83848C_ID         0x20005C90  /* PHY Identifier                    */\r
-\r
-/* DP83848C PHY Registers */\r
-#define PHY_REG_BMCR        0x00        /* Basic Mode Control Register       */\r
-#define PHY_REG_BMSR        0x01        /* Basic Mode Status Register        */\r
-#define PHY_REG_IDR1        0x02        /* PHY Identifier 1                  */\r
-#define PHY_REG_IDR2        0x03        /* PHY Identifier 2                  */\r
-#define PHY_REG_ANAR        0x04        /* Auto-Negotiation Advertisement    */\r
-#define PHY_REG_ANLPAR      0x05        /* Auto-Neg. Link Partner Abitily    */\r
-#define PHY_REG_ANER        0x06        /* Auto-Neg. Expansion Register      */\r
-#define PHY_REG_ANNPTR      0x07        /* Auto-Neg. Next Page TX            */\r
-\r
-/* PHY Extended Registers */\r
-#define PHY_REG_STS         0x10        /* Status Register                   */\r
-#define PHY_REG_MICR        0x11        /* MII Interrupt Control Register    */\r
-#define PHY_REG_MISR        0x12        /* MII Interrupt Status Register     */\r
-#define PHY_REG_FCSCR       0x14        /* False Carrier Sense Counter       */\r
-#define PHY_REG_RECR        0x15        /* Receive Error Counter             */\r
-#define PHY_REG_PCSR        0x16        /* PCS Sublayer Config. and Status   */\r
-#define PHY_REG_RBR         0x17        /* RMII and Bypass Register          */\r
-#define PHY_REG_LEDCR       0x18        /* LED Direct Control Register       */\r
-#define PHY_REG_PHYCR       0x19        /* PHY Control Register              */\r
-#define PHY_REG_10BTSCR     0x1A        /* 10Base-T Status/Control Register  */\r
-#define PHY_REG_CDCTRL1     0x1B        /* CD Test Control and BIST Extens.  */\r
-#define PHY_REG_EDCR        0x1D        /* Energy Detect Control Register    */\r
-\r
-#define PHY_FULLD_100M      0x2100      /* Full Duplex 100Mbit               */\r
-#define PHY_HALFD_100M      0x2000      /* Half Duplex 100Mbit               */\r
-#define PHY_FULLD_10M       0x0100      /* Full Duplex 10Mbit                */\r
-#define PHY_HALFD_10M       0x0000      /* Half Duplex 10MBit                */\r
-#define PHY_AUTO_NEG        0x3000      /* Select Auto Negotiation           */\r
-#define PHY_AUTO_NEG_COMPLETE 0x0020   /* Auto negotiation have finished.   */\r
-#define ETHDEV_PHY_DEF_ADR    0x0100      /* Default PHY device address        */\r
-\r
 const NyLPC_TBool EthDev_DP83848C_getInterface(\r
        const struct TiEthernetDevice** o_dev);\r
 \r