return false;
}
+bool radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder)
+{
+ struct drm_device *dev = encoder->base.dev;
+ struct drm_radeon_private *dev_priv = dev->dev_private;
+ uint16_t dac_info;
+ uint8_t rev, bg, dac;
+
+ /* check CRT table */
+ dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
+ if (dac_info) {
+ rev = radeon_bios8(dev_priv, dac_info) & 0x3;
+ if (rev < 2) {
+ bg = radeon_bios8(dev_priv, dac_info + 0x2) & 0xf;
+ dac = (radeon_bios8(dev_priv, dac_info + 0x2) >> 4) & 0xf;
+ encoder->ps2_pdac_adj = (bg << 8) | (dac);
+
+ return true;
+ } else {
+ bg = radeon_bios8(dev_priv, dac_info + 0x2) & 0xf;
+ dac = radeon_bios8(dev_priv, dac_info + 0x3) & 0xf;
+ encoder->ps2_pdac_adj = (bg << 8) | (dac);
+
+ return true;
+ }
+
+ }
+
+ return false;
+}
+
bool radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder)
{
struct drm_device *dev = encoder->base.dev;
dev_priv->chip_family == CHIP_RS480) {
uint16_t lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
if (lcd_info) {
- uint16_t lcd_ddc_info = lcd_ddc_info = combios_get_table_offset(dev, COMBIOS_LCD_DDC_INFO_TABLE);
+ uint16_t lcd_ddc_info = combios_get_table_offset(dev, COMBIOS_LCD_DDC_INFO_TABLE);
mode_info->bios_connector[4].valid = true;
mode_info->bios_connector[4].connector_type = CONNECTOR_LVDS;
combios_parse_mmio_table(dev, table);
}
+
+void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev)
+{
+ struct drm_radeon_private *dev_priv = dev->dev_private;
+ uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch;
+
+ bios_0_scratch = RADEON_READ(RADEON_BIOS_0_SCRATCH);
+ bios_6_scratch = RADEON_READ(RADEON_BIOS_6_SCRATCH);
+ //bios_7_scratch = RADEON_READ(RADEON_BIOS_7_SCRATCH);
+
+ /* let the bios control the backlight */
+ bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN;
+
+ /* tell the bios not to handle mode switching */
+ bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS |
+ RADEON_ACC_MODE_CHANGE);
+
+ /* tell the bios a driver is loaded */
+ //bios_7_scratch |= RADEON_DRV_LOADED;
+
+ RADEON_WRITE(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
+ RADEON_WRITE(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
+ //RADEON_WRITE(RADEON_BIOS_7_SCRATCH, bios_7_scratch);
+}
+
+void
+radeon_combios_output_lock(struct drm_encoder *encoder, bool lock)
+{
+ struct drm_device *dev = encoder->dev;
+ struct drm_radeon_private *dev_priv = dev->dev_private;
+ uint32_t bios_6_scratch;
+
+ bios_6_scratch = RADEON_READ(RADEON_BIOS_6_SCRATCH);
+
+ if (lock)
+ bios_6_scratch |= RADEON_DRIVER_CRITICAL;
+ else
+ bios_6_scratch &= ~RADEON_DRIVER_CRITICAL;
+
+ RADEON_WRITE(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
+}