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Merge "Remove duplicate."
[android-x86/external-llvm.git] / llvm-tblgen-rules.mk
diff --git a/llvm-tblgen-rules.mk b/llvm-tblgen-rules.mk
index b91fde9..ba59471 100644 (file)
--- a/llvm-tblgen-rules.mk
+++ b/llvm-tblgen-rules.mk
@@ -12,15 +12,15 @@ endef
 ###########################################################
 
 # Set LOCAL_MODULE_CLASS to STATIC_LIBRARIES default (require
-# for macro local-intermediates-dir)
+# for macro local-generated-sources-dir)
 ifeq ($(LOCAL_MODULE_CLASS),)
        LOCAL_MODULE_CLASS := STATIC_LIBRARIES
 endif
 
 ifneq ($(strip $(TBLGEN_TABLES)),)
 
-intermediates := $(call local-intermediates-dir)
-tblgen_gen_tables := $(addprefix $(intermediates)/,$(TBLGEN_TABLES))
+generated_sources := $(call local-generated-sources-dir)
+tblgen_gen_tables := $(addprefix $(generated_sources)/,$(TBLGEN_TABLES))
 LOCAL_GENERATED_SOURCES += $(tblgen_gen_tables)
 
 tblgen_source_dir := $(LOCAL_PATH)
@@ -28,132 +28,182 @@ ifneq ($(TBLGEN_TD_DIR),)
 tblgen_source_dir := $(TBLGEN_TD_DIR)
 endif
 
+ifneq (,$(filter $(tblgen_source_dir),MCTargetDesc))
+tblgen_td_deps := $(tblgen_source_dir)/../*.td
+else
+tblgen_td_deps := $(tblgen_source_dir)/*.td
+endif
+tblgen_td_deps := $(wildcard $(tblgen_td_deps))
+
 #
 # The directory and the .td directory is not the same.
 #
 ifeq ($(tblgen_source_dir),$(LLVM_ROOT_PATH)/lib/Target/ARM/MCTargetDesc)
-$(intermediates)/%GenRegisterInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
-$(intermediates)/%GenRegisterInfo.inc: $(tblgen_source_dir)/../%.td $(TBLGEN)
+$(generated_sources)/%GenRegisterInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
+$(generated_sources)/%GenRegisterInfo.inc: $(tblgen_source_dir)/../%.td \
+                                       $(tblgen_td_deps) $(LLVM_TBLGEN)
        $(call transform-td-to-out, register-info)
 
-$(intermediates)/%GenInstrInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
-$(intermediates)/%GenInstrInfo.inc: $(tblgen_source_dir)/../%.td $(TBLGEN)
+$(generated_sources)/%GenInstrInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
+$(generated_sources)/%GenInstrInfo.inc: $(tblgen_source_dir)/../%.td \
+                                    $(tblgen_td_deps) $(LLVM_TBLGEN)
        $(call transform-td-to-out,instr-info)
 
-$(intermediates)/%GenSubtargetInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
-$(intermediates)/%GenSubtargetInfo.inc: $(tblgen_source_dir)/../%.td $(TBLGEN)
+$(generated_sources)/%GenSubtargetInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
+$(generated_sources)/%GenSubtargetInfo.inc: $(tblgen_source_dir)/../%.td \
+                                        $(tblgen_td_deps) $(LLVM_TBLGEN)
        $(call transform-td-to-out,subtarget)
 endif
 
 ifeq ($(tblgen_source_dir),$(LLVM_ROOT_PATH)/lib/Target/X86/MCTargetDesc)
-$(intermediates)/%GenRegisterInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
-$(intermediates)/%GenRegisterInfo.inc: $(tblgen_source_dir)/../%.td $(TBLGEN)
+$(generated_sources)/%GenRegisterInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
+$(generated_sources)/%GenRegisterInfo.inc: $(tblgen_source_dir)/../%.td \
+                                       $(tblgen_td_deps) $(LLVM_TBLGEN)
        $(call transform-td-to-out, register-info)
 
-$(intermediates)/%GenInstrInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
-$(intermediates)/%GenInstrInfo.inc: $(tblgen_source_dir)/../%.td $(TBLGEN)
+$(generated_sources)/%GenInstrInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
+$(generated_sources)/%GenInstrInfo.inc: $(tblgen_source_dir)/../%.td \
+                                    $(tblgen_td_deps) $(LLVM_TBLGEN)
        $(call transform-td-to-out,instr-info)
 
-$(intermediates)/%GenSubtargetInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
-$(intermediates)/%GenSubtargetInfo.inc: $(tblgen_source_dir)/../%.td $(TBLGEN)
+$(generated_sources)/%GenSubtargetInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
+$(generated_sources)/%GenSubtargetInfo.inc: $(tblgen_source_dir)/../%.td \
+                                        $(tblgen_td_deps) $(LLVM_TBLGEN)
+       $(call transform-td-to-out,subtarget)
+endif
+
+ifeq ($(tblgen_source_dir),$(LLVM_ROOT_PATH)/lib/Target/Mips/MCTargetDesc)
+$(generated_sources)/%GenRegisterInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
+$(generated_sources)/%GenRegisterInfo.inc: $(tblgen_source_dir)/../%.td \
+                                       $(tblgen_td_deps) $(LLVM_TBLGEN)
+       $(call transform-td-to-out, register-info)
+
+$(generated_sources)/%GenInstrInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
+$(generated_sources)/%GenInstrInfo.inc: $(tblgen_source_dir)/../%.td \
+                                    $(tblgen_td_deps) $(LLVM_TBLGEN)
+       $(call transform-td-to-out,instr-info)
+
+$(generated_sources)/%GenSubtargetInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
+$(generated_sources)/%GenSubtargetInfo.inc: $(tblgen_source_dir)/../%.td \
+                                        $(tblgen_td_deps) $(LLVM_TBLGEN)
        $(call transform-td-to-out,subtarget)
 endif
 
 
 ifneq ($(filter %GenRegisterInfo.inc,$(tblgen_gen_tables)),)
-$(intermediates)/%GenRegisterInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
-$(intermediates)/%GenRegisterInfo.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
+$(generated_sources)/%GenRegisterInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
+$(generated_sources)/%GenRegisterInfo.inc: $(tblgen_source_dir)/%.td \
+                                       $(tblgen_td_deps) $(LLVM_TBLGEN)
        $(call transform-td-to-out,register-info)
 endif
 
 ifneq ($(filter %GenInstrInfo.inc,$(tblgen_gen_tables)),)
-$(intermediates)/%GenInstrInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
-$(intermediates)/%GenInstrInfo.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
+$(generated_sources)/%GenInstrInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
+$(generated_sources)/%GenInstrInfo.inc: $(tblgen_source_dir)/%.td \
+                                    $(tblgen_td_deps) $(LLVM_TBLGEN)
        $(call transform-td-to-out,instr-info)
 endif
 
 ifneq ($(filter %GenAsmWriter.inc,$(tblgen_gen_tables)),)
-$(intermediates)/%GenAsmWriter.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
-$(intermediates)/%GenAsmWriter.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
+$(generated_sources)/%GenAsmWriter.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
+$(generated_sources)/%GenAsmWriter.inc: $(tblgen_source_dir)/%.td \
+                                    $(tblgen_td_deps) $(LLVM_TBLGEN)
        $(call transform-td-to-out,asm-writer)
 endif
 
 ifneq ($(filter %GenAsmWriter1.inc,$(tblgen_gen_tables)),)
-$(intermediates)/%GenAsmWriter1.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
-$(intermediates)/%GenAsmWriter1.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
+$(generated_sources)/%GenAsmWriter1.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
+$(generated_sources)/%GenAsmWriter1.inc: $(tblgen_source_dir)/%.td \
+                                     $(tblgen_td_deps) $(LLVM_TBLGEN)
        $(call transform-td-to-out,asm-writer -asmwriternum=1)
 endif
 
 ifneq ($(filter %GenAsmMatcher.inc,$(tblgen_gen_tables)),)
-$(intermediates)/%GenAsmMatcher.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
-$(intermediates)/%GenAsmMatcher.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
+$(generated_sources)/%GenAsmMatcher.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
+$(generated_sources)/%GenAsmMatcher.inc: $(tblgen_source_dir)/%.td \
+                                     $(tblgen_td_deps) $(LLVM_TBLGEN)
        $(call transform-td-to-out,asm-matcher)
 endif
 
+# TODO(srhines): Is this needed
 ifneq ($(filter %GenCodeEmitter.inc,$(tblgen_gen_tables)),)
-$(intermediates)/%GenCodeEmitter.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
-$(intermediates)/%GenCodeEmitter.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
+$(generated_sources)/%GenCodeEmitter.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
+$(generated_sources)/%GenCodeEmitter.inc: $(tblgen_source_dir)/%.td \
+                                      $(tblgen_td_deps) $(LLVM_TBLGEN)
        $(call transform-td-to-out,emitter)
 endif
 
 ifneq ($(filter %GenMCCodeEmitter.inc,$(tblgen_gen_tables)),)
-$(intermediates)/%GenMCCodeEmitter.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
-$(intermediates)/%GenMCCodeEmitter.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
-       $(call transform-td-to-out,emitter -mc-emitter)
+$(generated_sources)/%GenMCCodeEmitter.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
+$(generated_sources)/%GenMCCodeEmitter.inc: $(tblgen_source_dir)/%.td \
+                                        $(tblgen_td_deps) $(LLVM_TBLGEN)
+       $(call transform-td-to-out,emitter)
 endif
 
 ifneq ($(filter %GenMCPseudoLowering.inc,$(tblgen_gen_tables)),)
-$(intermediates)/%GenMCPseudoLowering.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
-$(intermediates)/%GenMCPseudoLowering.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
+$(generated_sources)/%GenMCPseudoLowering.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
+$(generated_sources)/%GenMCPseudoLowering.inc: $(tblgen_source_dir)/%.td \
+                                           $(tblgen_td_deps) $(LLVM_TBLGEN)
        $(call transform-td-to-out,pseudo-lowering)
 endif
 
 ifneq ($(filter %GenDAGISel.inc,$(tblgen_gen_tables)),)
-$(intermediates)/%GenDAGISel.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
-$(intermediates)/%GenDAGISel.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
+$(generated_sources)/%GenDAGISel.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
+$(generated_sources)/%GenDAGISel.inc: $(tblgen_source_dir)/%.td \
+                                  $(tblgen_td_deps) $(LLVM_TBLGEN)
        $(call transform-td-to-out,dag-isel)
 endif
 
 ifneq ($(filter %GenDisassemblerTables.inc,$(tblgen_gen_tables)),)
-$(intermediates)/%GenDisassemblerTables.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
-$(intermediates)/%GenDisassemblerTables.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
+$(generated_sources)/%GenDisassemblerTables.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
+$(generated_sources)/%GenDisassemblerTables.inc: $(tblgen_source_dir)/%.td \
+                                             $(tblgen_td_deps) $(LLVM_TBLGEN)
        $(call transform-td-to-out,disassembler)
 endif
 
 ifneq ($(filter %GenEDInfo.inc,$(tblgen_gen_tables)),)
-$(intermediates)/%GenEDInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
-$(intermediates)/%GenEDInfo.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
+$(generated_sources)/%GenEDInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
+$(generated_sources)/%GenEDInfo.inc: $(tblgen_source_dir)/%.td \
+                                 $(tblgen_td_deps) $(LLVM_TBLGEN)
        $(call transform-td-to-out,enhanced-disassembly-info)
 endif
 
 ifneq ($(filter %GenFastISel.inc,$(tblgen_gen_tables)),)
-$(intermediates)/%GenFastISel.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
-$(intermediates)/%GenFastISel.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
+$(generated_sources)/%GenFastISel.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
+$(generated_sources)/%GenFastISel.inc: $(tblgen_source_dir)/%.td \
+                                   $(tblgen_td_deps) $(LLVM_TBLGEN)
        $(call transform-td-to-out,fast-isel)
 endif
 
 ifneq ($(filter %GenSubtargetInfo.inc,$(tblgen_gen_tables)),)
-$(intermediates)/%GenSubtargetInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
-$(intermediates)/%GenSubtargetInfo.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
+$(generated_sources)/%GenSubtargetInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
+$(generated_sources)/%GenSubtargetInfo.inc: $(tblgen_source_dir)/%.td \
+                                        $(tblgen_td_deps) $(LLVM_TBLGEN)
        $(call transform-td-to-out,subtarget)
 endif
 
 ifneq ($(filter %GenCallingConv.inc,$(tblgen_gen_tables)),)
-$(intermediates)/%GenCallingConv.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
-$(intermediates)/%GenCallingConv.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
+$(generated_sources)/%GenCallingConv.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
+$(generated_sources)/%GenCallingConv.inc: $(tblgen_source_dir)/%.td \
+                                      $(tblgen_td_deps) $(LLVM_TBLGEN)
        $(call transform-td-to-out,callingconv)
 endif
 
 ifneq ($(filter %GenIntrinsics.inc,$(tblgen_gen_tables)),)
-$(intermediates)/%GenIntrinsics.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
-$(intermediates)/%GenIntrinsics.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
+$(generated_sources)/%GenIntrinsics.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
+$(generated_sources)/%GenIntrinsics.inc: $(tblgen_source_dir)/%.td \
+                                     $(tblgen_td_deps) $(LLVM_TBLGEN)
        $(call transform-td-to-out,tgt_intrinsics)
 endif
 
 ifneq ($(findstring ARMGenDecoderTables.inc,$(tblgen_gen_tables)),)
-$(intermediates)/ARMGenDecoderTables.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
-$(intermediates)/ARMGenDecoderTables.inc: $(tblgen_source_dir)/ARM.td $(TBLGEN)
+$(generated_sources)/ARMGenDecoderTables.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
+$(generated_sources)/ARMGenDecoderTables.inc: $(tblgen_source_dir)/ARM.td \
+                                          $(tblgen_td_deps) $(LLVM_TBLGEN)
        $(call transform-td-to-out,arm-decoder)
 endif
 
+# Reset local variables
+tblgen_td_deps :=
+
 endif
external/llvm
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