+2011-06-29 H.J. Lu <hongjiu.lu@intel.com>
+
+ * tilegx-opc.c (find_opcode): Replace "index" with "i".
+ * tilepro-opc.c (find_opcode): Likewise.
+
+2011-06-29 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * mips16-opc.c (jalrc, jrc): Move earlier in file.
+
+2011-06-21 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis.c (prefix_table): Re-indent PREFIX_VEX_0F388C and
+ PREFIX_VEX_0F388E.
+
+2011-06-17 Andreas Schwab <schwab@redhat.com>
+
+ * Makefile.am (MAINTAINERCLEANFILES): Move s390-opc.tab ...
+ (MOSTLYCLEANFILES): ... here.
+ * Makefile.in: Regenerate.
+
+2011-06-14 Alan Modra <amodra@gmail.com>
+
+ * Makefile.in: Regenerate.
+
+2011-06-13 Walter Lee <walt@tilera.com>
+
+ * Makefile.am (TARGET_LIBOPCODES_CFILES): Add tilegx-dis.c,
+ tilegx-opc.c, tilepro-dis.c, and tilepro-opc.c.
+ * Makefile.in: Regenerate.
+ * configure.in: Handle bfd_tilegx_arch and bfd_tilepro_arch.
+ * configure: Regenerate.
+ * disassemble.c (disassembler): Add ARCH_tilegx and ARCH_tilepro.
+ * po/POTFILES.in: Regenerate.
+ * tilegx-dis.c: New file.
+ * tilegx-opc.c: New file.
+ * tilepro-dis.c: New file.
+ * tilepro-opc.c: New file.
+
+2011-06-10 H.J. Lu <hongjiu.lu@intel.com>
+
+ AVX Programming Reference (June, 2011)
+ * i386-dis.c (XMGatherQ): New.
+ * i386-dis.c (EXxmm_mb): New.
+ (EXxmm_mb): Likewise.
+ (EXxmm_mw): Likewise.
+ (EXxmm_md): Likewise.
+ (EXxmm_mq): Likewise.
+ (EXxmmdw): Likewise.
+ (EXxmmqd): Likewise.
+ (VexGatherQ): Likewise.
+ (MVexVSIBDWpX): Likewise.
+ (MVexVSIBQWpX): Likewise.
+ (xmm_mb_mode): Likewise.
+ (xmm_mw_mode): Likewise.
+ (xmm_md_mode): Likewise.
+ (xmm_mq_mode): Likewise.
+ (xmmdw_mode): Likewise.
+ (xmmqd_mode): Likewise.
+ (ymmxmm_mode): Likewise.
+ (vex_vsib_d_w_dq_mode): Likewise.
+ (vex_vsib_q_w_dq_mode): Likewise.
+ (MOD_VEX_0F385A_PREFIX_2): Likewise.
+ (MOD_VEX_0F388C_PREFIX_2): Likewise.
+ (MOD_VEX_0F388E_PREFIX_2): Likewise.
+ (PREFIX_0F3882): Likewise.
+ (PREFIX_VEX_0F3816): Likewise.
+ (PREFIX_VEX_0F3836): Likewise.
+ (PREFIX_VEX_0F3845): Likewise.
+ (PREFIX_VEX_0F3846): Likewise.
+ (PREFIX_VEX_0F3847): Likewise.
+ (PREFIX_VEX_0F3858): Likewise.
+ (PREFIX_VEX_0F3859): Likewise.
+ (PREFIX_VEX_0F385A): Likewise.
+ (PREFIX_VEX_0F3878): Likewise.
+ (PREFIX_VEX_0F3879): Likewise.
+ (PREFIX_VEX_0F388C): Likewise.
+ (PREFIX_VEX_0F388E): Likewise.
+ (PREFIX_VEX_0F3890..PREFIX_VEX_0F3893): Likewise.
+ (PREFIX_VEX_0F38F5): Likewise.
+ (PREFIX_VEX_0F38F6): Likewise.
+ (PREFIX_VEX_0F3A00): Likewise.
+ (PREFIX_VEX_0F3A01): Likewise.
+ (PREFIX_VEX_0F3A02): Likewise.
+ (PREFIX_VEX_0F3A38): Likewise.
+ (PREFIX_VEX_0F3A39): Likewise.
+ (PREFIX_VEX_0F3A46): Likewise.
+ (PREFIX_VEX_0F3AF0): Likewise.
+ (VEX_LEN_0F3816_P_2): Likewise.
+ (VEX_LEN_0F3819_P_2): Likewise.
+ (VEX_LEN_0F3836_P_2): Likewise.
+ (VEX_LEN_0F385A_P_2_M_0): Likewise.
+ (VEX_LEN_0F38F5_P_0): Likewise.
+ (VEX_LEN_0F38F5_P_1): Likewise.
+ (VEX_LEN_0F38F5_P_3): Likewise.
+ (VEX_LEN_0F38F6_P_3): Likewise.
+ (VEX_LEN_0F38F7_P_1): Likewise.
+ (VEX_LEN_0F38F7_P_2): Likewise.
+ (VEX_LEN_0F38F7_P_3): Likewise.
+ (VEX_LEN_0F3A00_P_2): Likewise.
+ (VEX_LEN_0F3A01_P_2): Likewise.
+ (VEX_LEN_0F3A38_P_2): Likewise.
+ (VEX_LEN_0F3A39_P_2): Likewise.
+ (VEX_LEN_0F3A46_P_2): Likewise.
+ (VEX_LEN_0F3AF0_P_3): Likewise.
+ (VEX_W_0F3816_P_2): Likewise.
+ (VEX_W_0F3818_P_2): Likewise.
+ (VEX_W_0F3819_P_2): Likewise.
+ (VEX_W_0F3836_P_2): Likewise.
+ (VEX_W_0F3846_P_2): Likewise.
+ (VEX_W_0F3858_P_2): Likewise.
+ (VEX_W_0F3859_P_2): Likewise.
+ (VEX_W_0F385A_P_2_M_0): Likewise.
+ (VEX_W_0F3878_P_2): Likewise.
+ (VEX_W_0F3879_P_2): Likewise.
+ (VEX_W_0F3A00_P_2): Likewise.
+ (VEX_W_0F3A01_P_2): Likewise.
+ (VEX_W_0F3A02_P_2): Likewise.
+ (VEX_W_0F3A38_P_2): Likewise.
+ (VEX_W_0F3A39_P_2): Likewise.
+ (VEX_W_0F3A46_P_2): Likewise.
+ (MOD_VEX_0F3818_PREFIX_2): Removed.
+ (MOD_VEX_0F3819_PREFIX_2): Likewise.
+ (VEX_LEN_0F60_P_2..VEX_LEN_0F6D_P_2): Likewise.
+ (VEX_LEN_0F70_P_1..VEX_LEN_0F76_P_2): Likewise.
+ (VEX_LEN_0FD1_P_2..VEX_LEN_0FD5_P_2): Likewise.
+ (VEX_LEN_0FD7_P_2_M_1..VEX_LEN_0F3819_P_2_M_0): Likewise.
+ (VEX_LEN_0F381C_P_2..VEX_LEN_0F3840_P_2): Likewise.
+ (VEX_LEN_0F3A0E_P_2): Likewise.
+ (VEX_LEN_0F3A0F_P_2): Likewise.
+ (VEX_LEN_0F3A42_P_2): Likewise.
+ (VEX_LEN_0F3A4C_P_2): Likewise.
+ (VEX_W_0F3818_P_2_M_0): Likewise.
+ (VEX_W_0F3819_P_2_M_0): Likewise.
+ (prefix_table): Updated.
+ (three_byte_table): Likewise.
+ (vex_table): Likewise.
+ (vex_len_table): Likewise.
+ (vex_w_table): Likewise.
+ (mod_table): Likewise.
+ (putop): Handle "LW".
+ (intel_operand_size): Handle xmm_mb_mode, xmm_mw_mode,
+ xmm_md_mode, xmm_mq_mode, xmmdw_mode, xmmqd_mode, ymmxmm_mode,
+ vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode.
+ (OP_EX): Likewise.
+ (OP_E_memory): Handle vex_vsib_d_w_dq_mode and
+ vex_vsib_q_w_dq_mode.
+ (OP_XMM): Handle vex_vsib_q_w_dq_mode.
+ (OP_VEX): Likewise.
+
+ * i386-gen.c (cpu_flag_init): Add CpuAVX2 to CPU_ANY_SSE_FLAGS
+ and CPU_ANY_AVX_FLAGS. Add CPU_BMI2_FLAGS, CPU_LZCNT_FLAGS,
+ CPU_INVPCID_FLAGS and CPU_AVX2_FLAGS.
+ (cpu_flags): Add CpuAVX2, CpuBMI2, CpuLZCNT and CpuINVPCID.
+ (opcode_modifiers): Add VecSIB.
+
+ * i386-opc.h (CpuAVX2): New.
+ (CpuBMI2): Likewise.
+ (CpuLZCNT): Likewise.
+ (CpuINVPCID): Likewise.
+ (VecSIB128): Likewise.
+ (VecSIB256): Likewise.
+ (VecSIB): Likewise.
+ (i386_cpu_flags): Add cpuavx2, cpubmi2, cpulzcnt and cpuinvpcid.
+ (i386_opcode_modifier): Add vecsib.
+
+ * i386-opc.tbl: Add invpcid, AVX2 and BMI2 instructions.
+ * i386-init.h: Regenerated.
+ * i386-tbl.h: Likewise.
+
+2011-06-03 Quentin Neill <quentin.neill@amd.com>
+
+ * i386-gen.c (cpu_flag_init): Add CpuF16C to CPU_BDVER2_FLAGS.
+ * i386-init.h: Regenerated.
+
+2011-06-03 Nick Clifton <nickc@redhat.com>
+
+ PR binutils/12752
+ * arm-dis.c (print_insn_coprocessor): Use bfd_vma type for
+ computing address offsets.
+ (print_arm_address): Likewise.
+ (print_insn_arm): Likewise.
+ (print_insn_thumb16): Likewise.
+ (print_insn_thumb32): Likewise.
+
+2011-06-02 Jie Zhang <jie@codesourcery.com>
+ Nathan Sidwell <nathan@codesourcery.com>
+ Maciej Rozycki <macro@codesourcery.com>
+
+ * arm-dis.c (print_insn_coprocessor): Explicitly print #-0
+ as address offset.
+ (print_arm_address): Likewise. Elide positive #0 appropriately.
+ (print_insn_arm): Likewise.
+
+2011-06-02 Nick Clifton <nickc@redhat.com>
+
+ PR gas/12752
+ * arm-dis.c (print_insn_thumb32): Do not sign extend addresses
+ passed to print_address_func.
+
+2011-06-02 Nick Clifton <nickc@redhat.com>
+
+ * arm-dis.c: Fix spelling mistakes.
+ * op/opcodes.pot: Regenerate.
+
+2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
+
+ * s390-opc.c: Replace S390_OPERAND_REG_EVEN with
+ S390_OPERAND_REG_PAIR. Fix INSTR_RRF_0UFEF instruction type.
+ * s390-opc.txt: Fix cxr instruction type.
+
+2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
+
+ * s390-opc.c: Add new instruction types marking register pair
+ operands.
+ * s390-opc.txt: Match instructions having register pair operands
+ to the new instruction types.
+
+2011-05-19 Nick Clifton <nickc@redhat.com>
+
+ * v850-opc.c (cmpf.[sd]): Reverse the order of the reg1 and reg2
+ operands.
+
+2011-05-10 Quentin Neill <quentin.neill@amd.com>
+
+ * i386-gen.c (cpu_flag_init): Add new CPU_BDVER2_FLAGS.
+ * i386-init.h: Regenerated.
+
+2011-04-27 Nick Clifton <nickc@redhat.com>
+
+ * po/da.po: Updated Danish translation.
+
+2011-04-26 Anton Blanchard <anton@samba.org>
+
+ * ppc-opc.c: (powerpc_opcodes): Enable icswx for POWER7.
+
+2011-04-21 DJ Delorie <dj@redhat.com>
+
+ * rx-decode.opc (rx_decode_opcode): Set the syntax for multi-byte NOPs.
+ * rx-decode.c: Regenerate.
+
+2011-04-20 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-init.h: Regenerated.
+
+2011-04-19 Quentin Neill <quentin.neill@amd.com>
+
+ * i386-gen.c (cpu_flag_init): Remove 3dnow and 3dnowa bits
+ from bdver1 flags.
+
+2011-04-13 Nick Clifton <nickc@redhat.com>
+
+ * v850-dis.c (disassemble): Always print a closing square brace if
+ an opening square brace was printed.
+
+2011-04-12 Nick Clifton <nickc@redhat.com>
+
+ PR binutils/12534
+ * arm-dis.c (thumb32_opcodes): Add %L suffix to LDRD and STRD insn
+ patterns.
+ (print_insn_thumb32): Handle %L.
+
+2011-04-11 Julian Brown <julian@codesourcery.com>
+
+ * arm-dis.c (psr_name): Fix typo for BASEPRI_MAX.
+ (print_insn_thumb32): Add APSR bitmask support.
+
+2011-04-07 Paul Carroll<pcarroll@codesourcery.com>
+
+ * arm-dis.c (print_insn): init vars moved into private_data structure.
+
+2011-03-24 Mike Frysinger <vapier@gentoo.org>
+
+ * bfin-dis.c (decode_dsp32mac_0): Move MM zeroing down to MAC0 logic.
+
+2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
+
+ * avr-dis.c (avr_operand): Add opcode_str parameter. Check for
+ post-increment to support LPM Z+ instruction. Add support for 'E'
+ constraint for DES instruction.
+ (print_insn_avr): Adjust calls to avr_operand. Rename variable.
+
+2011-03-14 Richard Sandiford <richard.sandiford@linaro.org>
+
+ * arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code.
+
+2011-03-14 Richard Sandiford <richard.sandiford@linaro.org>
+
+ * arm-dis.c (get_sym_code_type): Don't check for STT_ARM_TFUNC.
+ Use branch types instead.
+ (print_insn): Likewise.
+
+2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * mips-opc.c (mips_builtin_opcodes): Correct register use
+ annotation of "alnv.ps".
+
+2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * mips-opc.c (mips_builtin_opcodes): Add "pref" macro.
+
+2011-02-22 Mike Frysinger <vapier@gentoo.org>
+
+ * bfin-dis.c (OUTS): Remove p NULL check and txt NUL check.
+
+2011-02-22 Mike Frysinger <vapier@gentoo.org>
+
+ * bfin-dis.c (print_insn_bfin): Change outf->fprintf_func to OUTS.
+
+2011-02-19 Mike Frysinger <vapier@gentoo.org>
+
+ * bfin-dis.c (saved_state): Mark static. Change a[01]x to ax[] and
+ a[01]w to aw[]. Delete ac0, ac0_copy, ac1, an, aq, av0, av0s, av1,
+ av1s, az, cc, v, v_copy, vs, rnd_mod, v_internal, pc, ticks, insts,
+ exception, end_of_registers, msize, memory, bfd_mach.
+ (CCREG, PCREG, A0XREG, A0WREG, A1XREG, A1WREG, LC0REG, LT0REG,
+ LB0REG, LC1REG, LT1REG, LB1REG): Delete
+ (AXREG, AWREG, LCREG, LTREG, LBREG): Define.
+ (get_allreg): Change to new defines. Fallback to abort().
+
+2011-02-14 Mike Frysinger <vapier@gentoo.org>
+
+ * bfin-dis.c: Add whitespace/parenthesis where needed.
+
+2011-02-14 Mike Frysinger <vapier@gentoo.org>
+
+ * bfin-dis.c (decode_LoopSetup_0): Return when reg is greater
+ than 7.
+
+2011-02-13 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
+
+ * configure: Regenerate.
+
+2011-02-13 Mike Frysinger <vapier@gentoo.org>
+
+ * bfin-dis.c (decode_dsp32alu_0): Fix typo with A1 reg.
+
+2011-02-13 Mike Frysinger <vapier@gentoo.org>
+
+ * bfin-dis.c (decode_dsp32mult_0): Add 1 to dst for mac1. Output
+ dregs only when P is set, and dregs_lo otherwise.
+
+2011-02-13 Mike Frysinger <vapier@gentoo.org>
+
+ * bfin-dis.c (decode_dsp32alu_0): Delete BYTEOP2M code.
+
+2011-02-12 Mike Frysinger <vapier@gentoo.org>
+
+ * bfin-dis.c (decode_pseudoDEBUG_0): Add space after PRNT.
+
+2011-02-12 Mike Frysinger <vapier@gentoo.org>
+
+ * bfin-dis.c (machine_registers): Delete REG_GP.
+ (reg_names): Delete "GP".
+ (decode_allregs): Change REG_GP to REG_LASTREG.
+
2011-02-12 Mike Frysinger <vapier@gentoo.org>
- * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
- M_IU): Define.
- (is_macmod_pmove, is_macmod_hmove): New functions.
+ * bfin-dis.c (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2,
+ M_IH, M_IU): Delete.
2011-02-11 Mike Frysinger <vapier@gentoo.org>
2011-02-09 Michael Snyder <msnyder@vmware.com>
- * i386-dis.c (OP_J): Parenthesize expression to prevent
+ * i386-dis.c (OP_J): Parenthesize expression to prevent
truncated addresses.
(print_insn): Fix indentation off-by-one.
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