+2009-11-11 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis.c (all_prefixes): New.
+ (ckprefix): Set all_prefixes.
+ (print_insn): Print all_prefixes instead of lock_prefix,
+ repz_prefix, repnz_prefix, addr_prefix and data_prefix.
+
+2009-11-11 Nick Clifton <nickc@redhat.com>
+
+ PR binutils/10924
+ * arm-dis.c (UNPREDICTABLE_INSTRUCTION): New macro.
+ (print_insn_arm): Extend %s format control code to check for
+ unpredictable addressing modes. Add support for %S format control
+ code which suppresses this check.
+ (W_BIT, I_BIT, U_BIT, P_BIT): New macros.
+ (WRITEBACK_BIT_SET, IMMEDIATE_BIT_SET, NEGATIVE_BIT_SET,
+ PRE_BIT_SET): New macros.
+ (print_insn_coprocessor): Use the new macros instead of magic
+ constants.
+ (print_arm_address): Likewise.
+ (pirnt_insn_arm): Likewise.
+ (print_insn_thumb32): Likewise.
+
+2009-11-11 Nick Clifton <nickc@redhat.com>
+
+ * po/id.po: Updated Indonesian translation.
+
+2009-11-10 Maxim Kuvyrkov <maxim@codesourcery.com>
+
+ * m68k-dis.c (print_insn_arg): Handle RGPIOBAR, ACR[4-7] and MBAR[01].
+
+2009-11-06 Sebastian Pop <sebastian.pop@amd.com>
+
+ * i386-dis.c (reg_table): Add XOP_8F_TABLE (XOP_09) to
+ reg_table[REG_8F][1]: for XOP instructions, ModRM.reg first points to
+ B.mm in the RXB.mmmmm byte, and so when B is set, we still should use
+ the xop_table.
+ (get_valid_dis386): Removed unused condition (from cut/n/paste) for
+ XOP instructions.
+
+2009-11-05 Sebastian Pop <sebastian.pop@amd.com>
+ Quentin Neill <quentin.neill@amd.com>
+
+ * opcodes/i386-dis.c (OP_LWPCB_E): New.
+ (OP_LWP_E): New.
+ (OP_LWP_I): New.
+ (USE_XOP_8F_TABLE): New.
+ (XOP_8F_TABLE): New.
+ (REG_XOP_LWPCB): New.
+ (REG_XOP_LWP): New.
+ (XOP_09): New.
+ (XOP_0A): New.
+ (reg_table): Redirect REG_8F to XOP_8F_TABLE.
+ Add entries for REG_XOP_LWPCB and REG_XOP_LWP.
+ (xop_table): New.
+ (get_valid_dis386): Handle USE_XOP_8F_TABLE.
+ Use the offsets VEX_0F, VEX_0F38, and VEX_0F3A instead of their values
+ to access to the vex_table.
+ (OP_LWPCB_E): New.
+ (OP_LWP_E): New.
+ (OP_LWP_I): New.
+ * opcodes/i386-gen.c (cpu_flag_init): Add CPU_LWP_FLAGS, CpuLWP.
+ (cpu_flags): Add CpuLWP.
+ (opcode_modifiers): Add VexLWP, XOP09, and XOP0A.
+ * opcodes/i386-opc.h (CpuLWP): New.
+ (i386_cpu_flags): Add bit cpulwp.
+ (VexLWP): New.
+ (XOP09): New.
+ (XOP0A): New.
+ (i386_opcode_modifier): Add vexlwp, xop09, and xop0a.
+ * opcodes/i386-opc.tbl (llwpcb): Added.
+ (lwpval): Added.
+ (lwpins): Added.
+
+2009-11-04 DJ Delorie <dj@redhat.com>
+
+ * rx-decode.opc (rx_decode_opcode) (mvtipl): Add.
+ (mvtcp, mvfcp, opecp): Remove.
+ * rx-decode.c: Regenerate.
+ * rx-dis.c (cpen): Remove.
+
+2009-11-03 Doug Evans <dje@sebabeach.org>
+
+ * m32c-desc.c: Regenerate.
+ * mep-desc.c: Regenerate.
+
+2009-11-02 Paul Brook <paul@codesourcery.com>
+
+ * arm-dis.c (coprocessor_opcodes): Update to use new feature flags.
+ Add VFPv4 instructions.
+
+2009-10-29 Sebastian Pop <sebastian.pop@amd.com>
+
+ * i386-dis.c (OP_VEX_FMA): Removed.
+ (VexFMA): Removed.
+ (Vex128FMA): Removed.
+ (prefix_table): First source operand of FMA4 insns is decoded
+ with Vex not with VexFMA.
+ (OP_EX_VexW): Second source operand is decoded with get_vex_imm8
+ when vex.w is set. Third source operand is decoded with
+
+2009-10-27 Alan Modra <amodra@bigpond.net.au>
+
+ * Makefile.am (HFILES): Remove cgen-ops.h and cgen-types.h.
+ * Makefile.in: Regenerate.
+ * po/POTFILES.in: Regenerate.
+
+2009-10-23 Doug Evans <dje@sebabeach.org>
+
+ * cgen-ops.h: Delete, moved to ../include/cgen/basic-ops.h.
+ * cgen-types.h: Delete, moved to ../include/cgen/basic-modes.h.
+ * cgen-bitset.c: Update.
+ * fr30-desc.h: Regenerate.
+ * frv-desc.h: Regenerate.
+ * ip2k-desc.h: Regenerate.
+ * iq2000-desc.h: Regenerate.
+ * lm32-desc.h: Regenerate.
+ * m32c-desc.h: Regenerate.
+ * m32c-opc.h: Regenerate.
+ * m32r-desc.h: Regenerate.
+ * mep-desc.h: Regenerate.
+ * mt-desc.h: Regenerate.
+ * openrisc-desc.h: Regenerate.
+ * xc16x-desc.h: Regenerate.
+ * xstormy16-desc.h: Regenerate.
+
+2009-10-22 DJ Delorie <dj@redhat.com>
+
+ * rx-decode.opc (decode_opcode): Fix flags for MUL, SUNTIL, and SWHILE.
+ * rx-decode.c: Regenerated.
+
+2009-10-20 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/10775
+ * i386-dis.c: Document LB, LS and LV macros.
+ (dis386): Use mov%LB, mov%LS and mov%LV on mov instruction
+ with the 64-bit displacement or immediate operand.
+ (putop): Handle LB, LS and LV macros.
+
+2009-10-18 Doug Evans <dje@sebabeach.org>
+
+ * lm32-opinst.c: Regenerate.
+ * m32c-desc.c: Regenerate.
+ * m32r-opinst.c: Regenerate.
+ * openrisc-ibld.c: Regenerate.
+ * xc16x-desc.c: Regenerate.
+ * xc16x-desc.h: Regenerate.
+
+2009-10-17 Doug Evans <dje@sebabeach.org>
+
+ * Makefile.am (CGEN_CPUS): Add iq2000, lm32.
+ (FR30_DEPS, FRV_DEPS, IQ2000_DEPS): Move so all cgen *_DEPS are
+ sorted alphabetically.
+ (stamp-fr30, stamp-frv, stamp-iq2000, stamp-xc16x): Move so all cgen
+ stamp-* rules are sorted alphabetically.
+ * Makefile.in: Regenerate.
+
+2009-10-16 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-opc.h: Use enum instead of nested macros.
+
+2009-10-16 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis.c: Simplify enums.
+
+2009-10-15 H.J. Lu <hongjiu.lu@intel.com>
+ Ineiev <ineiev@gmail.com>
+
+ PR binutils/10767
+ * i386-dis.c: Use enum instead of nested macros.
+
2009-10-15 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (MAX_BYTEMODE): Removed.
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