#include "drm_sarea.h"
#include "i915_drm.h"
#include "i915_drv.h"
+#include "intel_bios.h"
+#include "intel_drv.h"
/**
* i915_probe_agp - get AGP bootup configuration
return 0;
}
-/**
- * i915_driver_load - setup chip and create an initial config
- * @dev: DRM device
- * @flags: startup flags
- *
- * The driver load routine has to do several things:
- * - drive output discovery via intel_modeset_init()
- * - initialize the memory manager
- * - allocate initial config memory
- * - setup the DRM framebuffer with the allocated memory
- */
-int i915_driver_load(struct drm_device *dev, unsigned long flags)
+int i915_load_modeset_init(struct drm_device *dev)
{
- struct drm_i915_private *dev_priv;
+ struct drm_i915_private *dev_priv = dev->dev_private;
unsigned long agp_size, prealloc_size;
- int size, ret;
-
- dev_priv = drm_alloc(sizeof(struct drm_i915_private), DRM_MEM_DRIVER);
- if (dev_priv == NULL)
- return -ENOMEM;
-
- memset(dev_priv, 0, sizeof(struct drm_i915_private));
- dev->dev_private = (void *)dev_priv;
-// dev_priv->flags = flags;
-
- /* i915 has 4 more counters */
- dev->counters += 4;
- dev->types[6] = _DRM_STAT_IRQ;
- dev->types[7] = _DRM_STAT_PRIMARY;
- dev->types[8] = _DRM_STAT_SECONDARY;
- dev->types[9] = _DRM_STAT_DMA;
-
- if (IS_I9XX(dev)) {
- pci_read_config_dword(dev->pdev, 0x5C, &dev_priv->stolen_base);
- DRM_DEBUG("stolen base %p\n", (void*)dev_priv->stolen_base);
- }
-
- if (IS_I9XX(dev)) {
- dev_priv->mmiobase = drm_get_resource_start(dev, 0);
- dev_priv->mmiolen = drm_get_resource_len(dev, 0);
- dev->mode_config.fb_base =
- drm_get_resource_start(dev, 2) & 0xff000000;
- } else if (drm_get_resource_start(dev, 1)) {
- dev_priv->mmiobase = drm_get_resource_start(dev, 1);
- dev_priv->mmiolen = drm_get_resource_len(dev, 1);
- dev->mode_config.fb_base =
- drm_get_resource_start(dev, 0) & 0xff000000;
- } else {
- DRM_ERROR("Unable to find MMIO registers\n");
- return -ENODEV;
- }
-
- DRM_DEBUG("fb_base: 0x%08lx\n", dev->mode_config.fb_base);
-
- ret = drm_addmap(dev, dev_priv->mmiobase, dev_priv->mmiolen,
- _DRM_REGISTERS, _DRM_READ_ONLY|_DRM_DRIVER, &dev_priv->mmio_map);
- if (ret != 0) {
- DRM_ERROR("Cannot add mapping for MMIO registers\n");
- return ret;
- }
-
- /*
- * Initialize the memory manager for local and AGP space
- */
- drm_bo_driver_init(dev);
+ int size, ret = 0;
i915_probe_agp(dev->pdev, &agp_size, &prealloc_size);
printk("setting up %ld bytes of VRAM space\n", prealloc_size);
printk("setting up %ld bytes of TT space\n", (agp_size - prealloc_size));
- drm_bo_init_mm(dev, DRM_BO_MEM_VRAM, 0, prealloc_size >> PAGE_SHIFT, 1);
- drm_bo_init_mm(dev, DRM_BO_MEM_TT, prealloc_size >> PAGE_SHIFT, (agp_size - prealloc_size) >> PAGE_SHIFT, 1);
- I915_WRITE(LP_RING + RING_LEN, 0);
- I915_WRITE(LP_RING + RING_HEAD, 0);
- I915_WRITE(LP_RING + RING_TAIL, 0);
+ drm_bo_init_mm(dev, DRM_BO_MEM_VRAM, 0, prealloc_size >> PAGE_SHIFT, 1);
+ drm_bo_init_mm(dev, DRM_BO_MEM_TT, prealloc_size >> PAGE_SHIFT,
+ (agp_size - prealloc_size) >> PAGE_SHIFT, 1);
+ I915_WRITE(PRB0_CTL, 0);
+ I915_WRITE(PRB0_HEAD, 0);
+ I915_WRITE(PRB0_TAIL, 0);
size = PRIMARY_RINGBUFFER_SIZE;
ret = drm_buffer_object_create(dev, size, drm_bo_type_kernel,
- DRM_BO_FLAG_READ | DRM_BO_FLAG_WRITE |
- DRM_BO_FLAG_MEM_VRAM |
- DRM_BO_FLAG_NO_EVICT,
- DRM_BO_HINT_DONT_FENCE, 0x1, 0,
- &dev_priv->ring_buffer);
+ DRM_BO_FLAG_READ | DRM_BO_FLAG_WRITE |
+ DRM_BO_FLAG_MEM_VRAM |
+ DRM_BO_FLAG_NO_EVICT,
+ DRM_BO_HINT_DONT_FENCE, 0x1, 0,
+ &dev_priv->ring_buffer);
if (ret < 0) {
DRM_ERROR("Unable to allocate or pin ring buffer\n");
- return -EINVAL;
+ goto clean_mm;
}
/* remap the buffer object properly */
/* FIXME: need wrapper with PCI mem checks */
ret = drm_mem_reg_ioremap(dev, &dev_priv->ring_buffer->mem,
(void **) &dev_priv->ring.virtual_start);
- if (ret)
+ if (ret) {
DRM_ERROR("error mapping ring buffer: %d\n", ret);
+ goto destroy_ringbuffer;
+ }
DRM_DEBUG("ring start %08lX, %p, %08lX\n", dev_priv->ring.Start,
- dev_priv->ring.virtual_start, dev_priv->ring.Size);
-
- //
+ dev_priv->ring.virtual_start, dev_priv->ring.Size);
memset((void *)(dev_priv->ring.virtual_start), 0, dev_priv->ring.Size);
-
- I915_WRITE(LP_RING + RING_START, dev_priv->ring.Start);
- I915_WRITE(LP_RING + RING_LEN,
- ((dev_priv->ring.Size - 4096) & RING_NR_PAGES) |
+ I915_WRITE(PRB0_START, dev_priv->ring.Start);
+ I915_WRITE(PRB0_CTL, ((dev_priv->ring.Size - 4096) & RING_NR_PAGES) |
(RING_NO_REPORT | RING_VALID));
- /* We are using separate values as placeholders for mechanisms for
- * private backbuffer/depthbuffer usage.
- */
- dev_priv->use_mi_batchbuffer_start = 0;
-
/* Allow hardware batchbuffers unless told otherwise.
*/
dev_priv->allow_batchbuffer = 1;
+ dev_priv->max_validate_buffers = I915_MAX_VALIDATE_BUFFERS;
+ mutex_init(&dev_priv->cmdbuf_mutex);
/* Program Hardware Status Page */
if (!IS_G33(dev)) {
drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff);
if (!dev_priv->status_page_dmah) {
- dev->dev_private = (void *)dev_priv;
- i915_dma_cleanup(dev);
DRM_ERROR("Can not allocate hardware status page\n");
- return -ENOMEM;
+ ret = -ENOMEM;
+ goto destroy_ringbuffer;
}
dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr;
dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
- I915_WRITE(I915REG_HWS_PGA, dev_priv->dma_status_page);
+ I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
+ } else {
+ size = 4 * 1024;
+ ret = drm_buffer_object_create(dev, size,
+ drm_bo_type_kernel,
+ DRM_BO_FLAG_READ | DRM_BO_FLAG_WRITE |
+ DRM_BO_FLAG_MEM_VRAM |
+ DRM_BO_FLAG_NO_EVICT,
+ DRM_BO_HINT_DONT_FENCE, 0x1, 0,
+ &dev_priv->hws_bo);
+ if (ret < 0) {
+ DRM_ERROR("Unable to allocate or pin hw status page\n");
+ ret = -EINVAL;
+ goto destroy_ringbuffer;
+ }
+
+ dev_priv->status_gfx_addr =
+ dev_priv->hws_bo->offset & (0x1ffff << 12);
+ dev_priv->hws_map.offset = dev->agp->base +
+ dev_priv->hws_bo->offset;
+ dev_priv->hws_map.size = size;
+ dev_priv->hws_map.type= 0;
+ dev_priv->hws_map.flags= 0;
+ dev_priv->hws_map.mtrr = 0;
+
+ drm_core_ioremap(&dev_priv->hws_map, dev);
+ if (dev_priv->hws_map.handle == NULL) {
+ dev_priv->status_gfx_addr = 0;
+ DRM_ERROR("can not ioremap virtual addr for"
+ "G33 hw status page\n");
+ ret = -ENOMEM;
+ goto destroy_hws;
+ }
+ dev_priv->hw_status_page = dev_priv->hws_map.handle;
+ memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
+ I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
}
DRM_DEBUG("Enabled hardware status page\n");
dev_priv->wq = create_singlethread_workqueue("i915");
- if (dev_priv == 0) {
+ if (dev_priv->wq == 0) {
DRM_DEBUG("Error\n");
+ ret = -EINVAL;
+ goto destroy_hws;
}
+ ret = intel_init_bios(dev);
+ if (ret) {
+ DRM_ERROR("failed to find VBIOS tables\n");
+ ret = -ENODEV;
+ goto destroy_wq;
+ }
intel_modeset_init(dev);
- drm_initial_config(dev, false);
+ drm_helper_initial_config(dev, false);
+
+ dev->devname = kstrdup(DRIVER_NAME, GFP_KERNEL);
+ if (!dev->devname) {
+ ret = -ENOMEM;
+ goto modeset_cleanup;
+ }
+
+ ret = drm_irq_install(dev);
+ if (ret) {
+ kfree(dev->devname);
+ goto modeset_cleanup;
+ }
+ return 0;
+
+modeset_cleanup:
+ intel_modeset_cleanup(dev);
+destroy_wq:
+ destroy_workqueue(dev_priv->wq);
+destroy_hws:
+ if (!IS_G33(dev)) {
+ if (dev_priv->status_page_dmah)
+ drm_pci_free(dev, dev_priv->status_page_dmah);
+ } else {
+ if (dev_priv->hws_map.handle)
+ drm_core_ioremapfree(&dev_priv->hws_map, dev);
+ if (dev_priv->hws_bo)
+ drm_bo_usage_deref_unlocked(&dev_priv->hws_bo);
+ }
+ I915_WRITE(HWS_PGA, 0x1ffff000);
+destroy_ringbuffer:
+ if (dev_priv->ring.virtual_start)
+ drm_mem_reg_iounmap(dev, &dev_priv->ring_buffer->mem,
+ dev_priv->ring.virtual_start);
+ if (dev_priv->ring_buffer)
+ drm_bo_usage_deref_unlocked(&dev_priv->ring_buffer);
+clean_mm:
+ drm_bo_clean_mm(dev, DRM_BO_MEM_VRAM, 1);
+ drm_bo_clean_mm(dev, DRM_BO_MEM_TT, 1);
+ return ret;
+}
+
+/**
+ * i915_driver_load - setup chip and create an initial config
+ * @dev: DRM device
+ * @flags: startup flags
+ *
+ * The driver load routine has to do several things:
+ * - drive output discovery via intel_modeset_init()
+ * - initialize the memory manager
+ * - allocate initial config memory
+ * - setup the DRM framebuffer with the allocated memory
+ */
+int i915_driver_load(struct drm_device *dev, unsigned long flags)
+{
+ struct drm_i915_private *dev_priv;
+ int ret = 0;
- drm_mm_print(&dev->bm.man[DRM_BO_MEM_VRAM].manager, "VRAM");
- drm_mm_print(&dev->bm.man[DRM_BO_MEM_TT].manager, "TT");
+ dev_priv = drm_alloc(sizeof(struct drm_i915_private), DRM_MEM_DRIVER);
+ if (dev_priv == NULL)
+ return -ENOMEM;
- drm_irq_install(dev);
+ memset(dev_priv, 0, sizeof(struct drm_i915_private));
+ dev->dev_private = (void *)dev_priv;
+ dev_priv->dev = dev;
+
+ /* i915 has 4 more counters */
+ dev->counters += 4;
+ dev->types[6] = _DRM_STAT_IRQ;
+ dev->types[7] = _DRM_STAT_PRIMARY;
+ dev->types[8] = _DRM_STAT_SECONDARY;
+ dev->types[9] = _DRM_STAT_DMA;
+
+ if (IS_MOBILE(dev) || IS_I9XX(dev))
+ dev_priv->cursor_needs_physical = true;
+ else
+ dev_priv->cursor_needs_physical = false;
+
+ if (IS_I965G(dev) || IS_G33(dev))
+ dev_priv->cursor_needs_physical = false;
+
+ if (IS_I9XX(dev)) {
+ pci_read_config_dword(dev->pdev, 0x5C, &dev_priv->stolen_base);
+ DRM_DEBUG("stolen base %p\n", (void*)dev_priv->stolen_base);
+ }
+
+ if (IS_I9XX(dev)) {
+ dev_priv->mmiobase = drm_get_resource_start(dev, 0);
+ dev_priv->mmiolen = drm_get_resource_len(dev, 0);
+ dev->mode_config.fb_base =
+ drm_get_resource_start(dev, 2) & 0xff000000;
+ } else if (drm_get_resource_start(dev, 1)) {
+ dev_priv->mmiobase = drm_get_resource_start(dev, 1);
+ dev_priv->mmiolen = drm_get_resource_len(dev, 1);
+ dev->mode_config.fb_base =
+ drm_get_resource_start(dev, 0) & 0xff000000;
+ } else {
+ DRM_ERROR("Unable to find MMIO registers\n");
+ ret = -ENODEV;
+ goto free_priv;
+ }
+
+ DRM_DEBUG("fb_base: 0x%08lx\n", dev->mode_config.fb_base);
+
+ ret = drm_addmap(dev, dev_priv->mmiobase, dev_priv->mmiolen,
+ _DRM_REGISTERS, _DRM_KERNEL|_DRM_READ_ONLY|_DRM_DRIVER,
+ &dev_priv->mmio_map);
+ if (ret != 0) {
+ DRM_ERROR("Cannot add mapping for MMIO registers\n");
+ goto free_priv;
+ }
+
+ INIT_LIST_HEAD(&dev_priv->mm.active_list);
+ INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
+ INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
+ INIT_LIST_HEAD(&dev_priv->mm.request_list);
+ dev_priv->mm.retire_timer.function = i915_gem_retire_timeout;
+ dev_priv->mm.retire_timer.data = (unsigned long) dev;
+ init_timer_deferrable (&dev_priv->mm.retire_timer);
+ INIT_WORK(&dev_priv->mm.retire_task,
+ i915_gem_retire_handler);
+ INIT_WORK(&dev_priv->user_interrupt_task,
+ i915_user_interrupt_handler);
+ dev_priv->mm.next_gem_seqno = 1;
+
+#ifdef __linux__
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,25)
+ intel_init_chipset_flush_compat(dev);
+#endif
+#endif
+
+ if (drm_core_check_feature(dev, DRIVER_MODESET)) {
+ /*
+ * Initialize the memory manager for local and AGP space
+ */
+ ret = drm_bo_driver_init(dev);
+ if (ret) {
+ DRM_ERROR("fail to init memory manager for "
+ "local & AGP space\n");
+ goto out_rmmap;
+ }
+ ret = i915_load_modeset_init(dev);
+ if (ret < 0) {
+ DRM_ERROR("failed to init modeset\n");
+ goto driver_fini;
+ }
+ }
return 0;
+
+driver_fini:
+ drm_bo_driver_finish(dev);
+out_rmmap:
+ drm_rmmap(dev, dev_priv->mmio_map);
+free_priv:
+ drm_free(dev_priv, sizeof(struct drm_i915_private), DRM_MEM_DRIVER);
+ return ret;
}
int i915_driver_unload(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
- I915_WRITE(LP_RING + RING_LEN, 0);
+ I915_WRITE(PRB0_CTL, 0);
- intel_modeset_cleanup(dev);
+ if (drm_core_check_feature(dev, DRIVER_MODESET)) {
+ drm_irq_uninstall(dev);
+ intel_modeset_cleanup(dev);
+ destroy_workqueue(dev_priv->wq);
+ }
#if 0
if (dev_priv->ring.virtual_start) {
if (dev_priv->sarea_kmap.virtual) {
drm_bo_kunmap(&dev_priv->sarea_kmap);
dev_priv->sarea_kmap.virtual = NULL;
- dev->primary->master->lock.hw_lock = NULL;
dev->sigdata.lock = NULL;
}
dev_priv->hw_status_page = NULL;
dev_priv->dma_status_page = 0;
/* Need to rewrite hardware status page */
- I915_WRITE(I915REG_HWS_PGA, 0x1ffff000);
+ I915_WRITE(HWS_PGA, 0x1ffff000);
}
if (dev_priv->status_gfx_addr) {
dev_priv->status_gfx_addr = 0;
drm_core_ioremapfree(&dev_priv->hws_map, dev);
- I915_WRITE(I915REG_HWS_PGA, 0x1ffff000);
+ drm_bo_usage_deref_unlocked(&dev_priv->hws_bo);
+ I915_WRITE(HWS_PGA, 0x1ffff000);
}
- drm_mem_reg_iounmap(dev, &dev_priv->ring_buffer->mem,
- dev_priv->ring.virtual_start);
+ if (drm_core_check_feature(dev, DRIVER_MODESET)) {
+ drm_mem_reg_iounmap(dev, &dev_priv->ring_buffer->mem,
+ dev_priv->ring.virtual_start);
- DRM_DEBUG("usage is %d\n", atomic_read(&dev_priv->ring_buffer->usage));
- mutex_lock(&dev->struct_mutex);
- drm_bo_usage_deref_locked(&dev_priv->ring_buffer);
+ DRM_DEBUG("usage is %d\n", atomic_read(&dev_priv->ring_buffer->usage));
+ mutex_lock(&dev->struct_mutex);
+ drm_bo_usage_deref_locked(&dev_priv->ring_buffer);
- if (drm_bo_clean_mm(dev, DRM_BO_MEM_TT, 1)) {
- DRM_ERROR("Memory manager type 3 not clean. "
- "Delaying takedown\n");
- }
- if (drm_bo_clean_mm(dev, DRM_BO_MEM_VRAM, 1)) {
- DRM_ERROR("Memory manager type 3 not clean. "
- "Delaying takedown\n");
+ if (drm_bo_clean_mm(dev, DRM_BO_MEM_TT, 1)) {
+ DRM_ERROR("Memory manager type 3 not clean. "
+ "Delaying takedown\n");
+ }
+ if (drm_bo_clean_mm(dev, DRM_BO_MEM_VRAM, 1)) {
+ DRM_ERROR("Memory manager type 3 not clean. "
+ "Delaying takedown\n");
+ }
+ mutex_unlock(&dev->struct_mutex);
}
- mutex_unlock(&dev->struct_mutex);
drm_bo_driver_finish(dev);
+#ifdef __linux__
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,25)
+ intel_init_chipset_flush_compat(dev);
+#endif
+#endif
+
DRM_DEBUG("%p\n", dev_priv->mmio_map);
drm_rmmap(dev, dev_priv->mmio_map);
if (!master_priv)
return;
- drm_rmmap(dev, master_priv->sarea);
+ if (master_priv->sarea)
+ drm_rmmap(dev, master_priv->sarea);
+
drm_free(master_priv, sizeof(*master_priv), DRM_MEM_DRIVER);
master->driver_priv = NULL;
}
+
+void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ if (!drm_core_check_feature(dev, DRIVER_MODESET))
+ i915_mem_release(dev, file_priv, dev_priv->agp_heap);
+}
+
+void i915_driver_lastclose(struct drm_device * dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+
+ if (drm_core_check_feature(dev, DRIVER_MODESET))
+ return;
+
+#ifdef I915_HAVE_BUFFER
+ if (dev_priv->val_bufs) {
+ vfree(dev_priv->val_bufs);
+ dev_priv->val_bufs = NULL;
+ }
+#endif
+
+ i915_gem_lastclose(dev);
+
+ if (dev_priv->agp_heap)
+ i915_mem_takedown(&(dev_priv->agp_heap));
+
+#if defined(I915_HAVE_BUFFER)
+ if (dev_priv->sarea_kmap.virtual) {
+ drm_bo_kunmap(&dev_priv->sarea_kmap);
+ dev_priv->sarea_kmap.virtual = NULL;
+ dev->control->master->lock.hw_lock = NULL;
+ dev->sigdata.lock = NULL;
+ }
+
+ if (dev_priv->sarea_bo) {
+ mutex_lock(&dev->struct_mutex);
+ drm_bo_usage_deref_locked(&dev_priv->sarea_bo);
+ mutex_unlock(&dev->struct_mutex);
+ dev_priv->sarea_bo = NULL;
+ }
+#endif
+
+ i915_dma_cleanup(dev);
+}
+
+int i915_driver_firstopen(struct drm_device *dev)
+{
+ if (drm_core_check_feature(dev, DRIVER_MODESET))
+ return 0;
+
+ drm_bo_driver_init(dev);
+ return 0;
+}
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