radeon: Add support for HD2100 IGP (RS740)

[android-x86/external-libdrm.git] / shared-core / radeon_cp.c

diff --git a/shared-core/radeon_cp.c b/shared-core/radeon_cp.c
index 7317d18..7e454fb 100644 (file)
--- a/shared-core/radeon_cp.c
+++ b/shared-core/radeon_cp.c
@@ -39,6 +39,7 @@
 #define RADEON_FIFO_DEBUG      0
 
 static int radeon_do_cleanup_cp(struct drm_device * dev);
+static void radeon_do_cp_start(drm_radeon_private_t * dev_priv);
 
 static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
 {
@@ -69,7 +70,8 @@ static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
 
 static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
 {
-        if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
+       if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
+           ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
            return RS690_READ_MCIND(dev_priv, addr);
        else
            return RS480_READ_MCIND(dev_priv, addr);
@@ -80,7 +82,8 @@ u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
 
        if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
                return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
-       else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
+       else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
+                ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
                return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION);
        else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
                return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
@@ -92,7 +95,8 @@ static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
 {
        if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
                R500_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
-       else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
+       else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
+                ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
                RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc);
        else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
                R500_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);
@@ -104,7 +108,8 @@ static void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_lo
 {
        if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
                R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
-       else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
+       else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
+                ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
                RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc);
        else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
                R500_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
@@ -120,7 +125,8 @@ static void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
        if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) {
                R500_WRITE_MCIND(RV515_MC_AGP_BASE, agp_base_lo);
                R500_WRITE_MCIND(RV515_MC_AGP_BASE_2, agp_base_hi);
-       } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) {
+       } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
+                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
                RS690_WRITE_MCIND(RS690_MC_AGP_BASE, agp_base_lo);
                RS690_WRITE_MCIND(RS690_MC_AGP_BASE_2, agp_base_hi);
        } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) {
@@ -198,23 +204,8 @@ static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
                        DRM_UDELAY(1);
                }
        } else {
-               /* 3D */
-               tmp = RADEON_READ(R300_RB3D_DSTCACHE_CTLSTAT);
-               tmp |= RADEON_RB3D_DC_FLUSH_ALL;
-               RADEON_WRITE(R300_RB3D_DSTCACHE_CTLSTAT, tmp);
-
-               /* 2D */
-               tmp = RADEON_READ(R300_DSTCACHE_CTLSTAT);
-               tmp |= RADEON_RB3D_DC_FLUSH_ALL;
-               RADEON_WRITE(R300_DSTCACHE_CTLSTAT, tmp);
-
-               for (i = 0; i < dev_priv->usec_timeout; i++) {
-                       if (!(RADEON_READ(R300_DSTCACHE_CTLSTAT)
-                         & RADEON_RB3D_DC_BUSY)) {
-                               return 0;
-                       }
-                       DRM_UDELAY(1);
-               }
+               /* don't flush or purge cache here or lockup */
+               return 0;
        }
 
 #if RADEON_FIFO_DEBUG
@@ -237,6 +228,9 @@ static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
                        return 0;
                DRM_UDELAY(1);
        }
+       DRM_INFO("wait for fifo failed status : 0x%08X 0x%08X\n",
+                RADEON_READ(RADEON_RBBM_STATUS),
+                RADEON_READ(R300_VAP_CNTL_STATUS));
 
 #if RADEON_FIFO_DEBUG
        DRM_ERROR("failed!\n");
@@ -263,6 +257,9 @@ static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
                }
                DRM_UDELAY(1);
        }
+       DRM_INFO("wait idle failed status : 0x%08X 0x%08X\n",
+                RADEON_READ(RADEON_RBBM_STATUS),
+                RADEON_READ(R300_VAP_CNTL_STATUS));
 
 #if RADEON_FIFO_DEBUG
        DRM_ERROR("failed!\n");
@@ -374,8 +371,9 @@ static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
                        RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
                                     R420_cp_microcode[i][0]);
                }
-       } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) {
-               DRM_INFO("Loading RS690 Microcode\n");
+       } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
+                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
+               DRM_INFO("Loading RS690/RS740 Microcode\n");
                for (i = 0; i < 256; i++) {
                        RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
                                     RS690_cp_microcode[i][1]);
@@ -445,14 +443,20 @@ static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
 
        dev_priv->cp_running = 1;
 
-       BEGIN_RING(6);
-
+       BEGIN_RING(8);
+       /* isync can only be written through cp on r5xx write it here */
+       OUT_RING(CP_PACKET0(RADEON_ISYNC_CNTL, 0));
+       OUT_RING(RADEON_ISYNC_ANY2D_IDLE3D |
+                RADEON_ISYNC_ANY3D_IDLE2D |
+                RADEON_ISYNC_WAIT_IDLEGUI |
+                RADEON_ISYNC_CPSCRATCH_IDLEGUI);
        RADEON_PURGE_CACHE();
        RADEON_PURGE_ZCACHE();
        RADEON_WAIT_UNTIL_IDLE();
-
        ADVANCE_RING();
        COMMIT_RING();
+
+       dev_priv->track_flush |= RADEON_FLUSH_EMITED | RADEON_PURGE_EMITED;
 }
 
 /* Reset the Command Processor.  This will not flush any pending
@@ -630,9 +634,6 @@ static void radeon_cp_init_ring_buffer(struct drm_device * dev,
                     dev_priv->ring.size_l2qw);
 #endif
 
-       /* Start with assuming that writeback doesn't work */
-       dev_priv->writeback_works = 0;
-
        /* Initialize the scratch register pointer.  This will cause
         * the scratch register values to be written out to memory
         * whenever they are updated.
@@ -723,7 +724,8 @@ static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
 
                temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL);
 
-               if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
+               if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
+                   ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
                        IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, (RS480_GART_INDEX_REG_EN |
                                                             RS690_BLOCK_GFX_D3_EN));
                else
@@ -816,6 +818,7 @@ static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
        u32 tmp;
 
        if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
+           ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740) ||
            (dev_priv->flags & RADEON_IS_IGPGART)) {
                radeon_set_igpgart(dev_priv, on);
                return;
@@ -895,17 +898,6 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
         */
        dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
 
-       switch(init->func) {
-       case RADEON_INIT_R200_CP:
-               dev_priv->microcode_version = UCODE_R200;
-               break;
-       case RADEON_INIT_R300_CP:
-               dev_priv->microcode_version = UCODE_R300;
-               break;
-       default:
-               dev_priv->microcode_version = UCODE_R100;
-       }
-
        dev_priv->do_boxes = 0;
        dev_priv->cp_mode = init->cp_mode;
 
@@ -953,8 +945,7 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
         */
        dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
                                           (dev_priv->color_fmt << 10) |
-                                          (dev_priv->microcode_version ==
-                                           UCODE_R100 ? RADEON_ZBLOCK16 : 0));
+                                          (dev_priv->chip_family < CHIP_R200 ? RADEON_ZBLOCK16 : 0));
 
        dev_priv->depth_clear.rb3d_zstencilcntl =
            (dev_priv->depth_fmt |
@@ -1160,7 +1151,7 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
                        dev_priv->gart_info.mapping.size =
                            dev_priv->gart_info.table_size;
 
-                       drm_core_ioremap(&dev_priv->gart_info.mapping, dev);
+                       drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev);
                        dev_priv->gart_info.addr =
                            dev_priv->gart_info.mapping.handle;
 
@@ -1201,6 +1192,9 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
                radeon_set_pcigart(dev_priv, 1);
        }
 
+       /* Start with assuming that writeback doesn't work */
+       dev_priv->writeback_works = 0;
+
        radeon_cp_load_microcode(dev_priv);
        radeon_cp_init_ring_buffer(dev, dev_priv);
 
@@ -1733,6 +1727,7 @@ int radeon_driver_load(struct drm_device *dev, unsigned long flags)
                break;
        }
 
+       dev_priv->chip_family = flags & RADEON_FAMILY_MASK;
        if (drm_device_is_agp(dev))
                dev_priv->flags |= RADEON_IS_AGP;
        else if (drm_device_is_pcie(dev))