Merge branch 'radeon-gem-cs' into modesetting-gem

[android-x86/external-libdrm.git] / shared-core / radeon_drv.h

diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h
index 2b8d7f6..a40ff6d 100644 (file)
--- a/shared-core/radeon_drv.h
+++ b/shared-core/radeon_drv.h
@@ -39,7 +39,7 @@
 
 #define DRIVER_NAME            "radeon"
 #define DRIVER_DESC            "ATI Radeon"
-#define DRIVER_DATE            "20080528"
+#define DRIVER_DATE            "20080613"
 
 /* Interface history:
  *
@@ -289,6 +289,9 @@ struct drm_radeon_master_private {
        drm_radeon_sarea_t *sarea_priv;
 };
 
+#define RADEON_FLUSH_EMITED    (1 < 0)
+#define RADEON_PURGE_EMITED    (1 < 1)
+
 /* command submission struct */
 struct drm_radeon_cs_priv {
        uint32_t id_wcnt;
@@ -387,7 +390,6 @@ typedef struct drm_radeon_private {
        struct radeon_surface surfaces[RADEON_MAX_SURFACES];
        struct radeon_virt_surface virt_surfaces[2 * RADEON_MAX_SURFACES];
 
-
        u32 scratch_ages[5];
 
        unsigned int crtc_last_cnt;
@@ -397,13 +399,10 @@ typedef struct drm_radeon_private {
        uint32_t flags;         /* see radeon_chip_flags */
        unsigned long fb_aper_offset;
 
-       int num_gb_pipes;
-
        bool mm_enabled;
        struct radeon_mm_info mm;
        drm_local_map_t *mmio;
 
-       uint32_t chip_family;
 
        unsigned long pcigart_offset;
        unsigned int pcigart_offset_set;
@@ -420,6 +419,10 @@ typedef struct drm_radeon_private {
        u32 ram_width;
 
        enum radeon_pll_errata pll_errata;
+       
+       int num_gb_pipes;
+       int track_flush;
+       uint32_t chip_family; /* extract from flags */
 
        struct radeon_mm_obj **ib_objs;
        /* ib bitmap */
@@ -485,6 +488,7 @@ extern void radeon_mem_release(struct drm_file *file_priv,
                               struct mem_block *heap);
 
                                /* radeon_irq.c */
+extern void radeon_irq_set_state(struct drm_device *dev, u32 mask, int state);
 extern int radeon_irq_emit(struct drm_device *dev, void *data, struct drm_file *file_priv);
 extern int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_priv);
 
@@ -779,11 +783,6 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
 #define RADEON_PP_TXFILTER_1           0x1c6c
 #define RADEON_PP_TXFILTER_2           0x1c84
 
-#define RADEON_RB2D_DSTCACHE_CTLSTAT   0x342c
-#      define RADEON_RB2D_DC_FLUSH             (3 << 0)
-#      define RADEON_RB2D_DC_FREE              (3 << 2)
-#      define RADEON_RB2D_DC_FLUSH_ALL         0xf
-#      define RADEON_RB2D_DC_BUSY              (1 << 31)
 #define RADEON_RB3D_CNTL               0x1c3c
 #      define RADEON_ALPHA_BLEND_ENABLE        (1 << 0)
 #      define RADEON_PLANE_MASK_ENABLE         (1 << 1)
@@ -809,9 +808,10 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
 #define R300_ZB_ZCACHE_CTLSTAT                  0x4f18
 #      define R300_ZC_FLUSH                    (1 << 0)
 #      define R300_ZC_FREE                     (1 << 1)
-#      define R300_ZC_FLUSH_ALL                0x3
 #      define R300_ZC_BUSY                     (1 << 31)
 #define R300_RB3D_DSTCACHE_CTLSTAT              0x4e4c
+#      define R300_RB3D_DC_FLUSH               (2 << 0)
+#      define R300_RB3D_DC_FREE                (2 << 2)
 #      define R300_RB3D_DC_FINISH              (1 << 4)
 #define RADEON_RB3D_ZSTENCILCNTL       0x1c2c
 #      define RADEON_Z_TEST_MASK               (7 << 4)
@@ -1387,10 +1387,10 @@ do {                                                                    \
 #define RADEON_PURGE_CACHE() do {                                      \
        if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {     \
                OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));  \
-               OUT_RING(RADEON_RB3D_DC_FLUSH_ALL);                     \
+               OUT_RING(RADEON_RB3D_DC_FLUSH | RADEON_RB3D_DC_FREE);   \
        } else {                                                        \
                OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));    \
-               OUT_RING(RADEON_RB3D_DC_FLUSH_ALL);                     \
+               OUT_RING(R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE );      \
        }                                                               \
 } while (0)
 
@@ -1407,10 +1407,10 @@ do {                                                                    \
 #define RADEON_PURGE_ZCACHE() do {                                     \
        if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {     \
                OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));    \
-               OUT_RING(RADEON_RB3D_ZC_FLUSH_ALL);                     \
+               OUT_RING(RADEON_RB3D_ZC_FLUSH | RADEON_RB3D_ZC_FREE);   \
        } else {                                                        \
-               OUT_RING(CP_PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));      \
-               OUT_RING(R300_ZC_FLUSH_ALL);                            \
+               OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0));        \
+               OUT_RING(R300_ZC_FLUSH | R300_ZC_FREE);                 \
        }                                                               \
 } while (0)