Regenerate cgen files, update copyright year.

[pf3gnuchains/pf3gnuchains3x.git] / sid / component / cgen-cpu / mep / mep-cop1-32-decode.cxx

diff --git a/sid/component/cgen-cpu/mep/mep-cop1-32-decode.cxx b/sid/component/cgen-cpu/mep/mep-cop1-32-decode.cxx
index 7923714..423d5db 100644 (file)
--- a/sid/component/cgen-cpu/mep/mep-cop1-32-decode.cxx
+++ b/sid/component/cgen-cpu/mep/mep-cop1-32-decode.cxx
@@ -2,7 +2,7 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright (C) 2000-2007 Red Hat, Inc.
+Copyright (C) 2000-2010 Red Hat, Inc.
 
 This file is part of the Red Hat simulators.
 
@@ -22,300 +22,300 @@ using namespace mep_ext1; // FIXME: namespace organization still wip
 
 mepcop1_32_idesc mepcop1_32_idesc::idesc_table[MEPCOP1_32_INSN_CPSMSBSLLA1_W_C3 + 1] =
 {
-  { mepcop1_32_sem_x_invalid, "X_INVALID", MEPCOP1_32_INSN_X_INVALID, { 0|(1<<CGEN_INSN_VIRTUAL), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
-  { mepcop1_32_sem_cmov_crn_rm, "CMOV_CRN_RM", MEPCOP1_32_INSN_CMOV_CRN_RM, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cmov_rn_crm, "CMOV_RN_CRM", MEPCOP1_32_INSN_CMOV_RN_CRM, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cmovc_ccrn_rm, "CMOVC_CCRN_RM", MEPCOP1_32_INSN_CMOVC_CCRN_RM, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cmovc_rn_ccrm, "CMOVC_RN_CCRM", MEPCOP1_32_INSN_CMOVC_RN_CCRM, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cmovh_crn_rm, "CMOVH_CRN_RM", MEPCOP1_32_INSN_CMOVH_CRN_RM, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cmovh_rn_crm, "CMOVH_RN_CRM", MEPCOP1_32_INSN_CMOVH_RN_CRM, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpadd3_b_C3, "CPADD3_B_C3", MEPCOP1_32_INSN_CPADD3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpadd3_h_C3, "CPADD3_H_C3", MEPCOP1_32_INSN_CPADD3_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpadd3_w_C3, "CPADD3_W_C3", MEPCOP1_32_INSN_CPADD3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cdadd3_C3, "CDADD3_C3", MEPCOP1_32_INSN_CDADD3_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpsub3_b_C3, "CPSUB3_B_C3", MEPCOP1_32_INSN_CPSUB3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpsub3_h_C3, "CPSUB3_H_C3", MEPCOP1_32_INSN_CPSUB3_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpsub3_w_C3, "CPSUB3_W_C3", MEPCOP1_32_INSN_CPSUB3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cdsub3_C3, "CDSUB3_C3", MEPCOP1_32_INSN_CDSUB3_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpand3_C3, "CPAND3_C3", MEPCOP1_32_INSN_CPAND3_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpor3_C3, "CPOR3_C3", MEPCOP1_32_INSN_CPOR3_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpnor3_C3, "CPNOR3_C3", MEPCOP1_32_INSN_CPNOR3_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpxor3_C3, "CPXOR3_C3", MEPCOP1_32_INSN_CPXOR3_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpsel_C3, "CPSEL_C3", MEPCOP1_32_INSN_CPSEL_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpfsftbi_C3, "CPFSFTBI_C3", MEPCOP1_32_INSN_CPFSFTBI_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpfsftbs0_C3, "CPFSFTBS0_C3", MEPCOP1_32_INSN_CPFSFTBS0_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpfsftbs1_C3, "CPFSFTBS1_C3", MEPCOP1_32_INSN_CPFSFTBS1_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpunpacku_b_C3, "CPUNPACKU_B_C3", MEPCOP1_32_INSN_CPUNPACKU_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpunpacku_h_C3, "CPUNPACKU_H_C3", MEPCOP1_32_INSN_CPUNPACKU_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpunpacku_w_C3, "CPUNPACKU_W_C3", MEPCOP1_32_INSN_CPUNPACKU_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpunpackl_b_C3, "CPUNPACKL_B_C3", MEPCOP1_32_INSN_CPUNPACKL_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpunpackl_h_C3, "CPUNPACKL_H_C3", MEPCOP1_32_INSN_CPUNPACKL_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpunpackl_w_C3, "CPUNPACKL_W_C3", MEPCOP1_32_INSN_CPUNPACKL_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cppacku_b_C3, "CPPACKU_B_C3", MEPCOP1_32_INSN_CPPACKU_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cppack_b_C3, "CPPACK_B_C3", MEPCOP1_32_INSN_CPPACK_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cppack_h_C3, "CPPACK_H_C3", MEPCOP1_32_INSN_CPPACK_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpsrl3_b_C3, "CPSRL3_B_C3", MEPCOP1_32_INSN_CPSRL3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpssrl3_b_C3, "CPSSRL3_B_C3", MEPCOP1_32_INSN_CPSSRL3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpsrl3_h_C3, "CPSRL3_H_C3", MEPCOP1_32_INSN_CPSRL3_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpssrl3_h_C3, "CPSSRL3_H_C3", MEPCOP1_32_INSN_CPSSRL3_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpsrl3_w_C3, "CPSRL3_W_C3", MEPCOP1_32_INSN_CPSRL3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpssrl3_w_C3, "CPSSRL3_W_C3", MEPCOP1_32_INSN_CPSSRL3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cdsrl3_C3, "CDSRL3_C3", MEPCOP1_32_INSN_CDSRL3_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpsra3_b_C3, "CPSRA3_B_C3", MEPCOP1_32_INSN_CPSRA3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpssra3_b_C3, "CPSSRA3_B_C3", MEPCOP1_32_INSN_CPSSRA3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpsra3_h_C3, "CPSRA3_H_C3", MEPCOP1_32_INSN_CPSRA3_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpssra3_h_C3, "CPSSRA3_H_C3", MEPCOP1_32_INSN_CPSSRA3_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpsra3_w_C3, "CPSRA3_W_C3", MEPCOP1_32_INSN_CPSRA3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpssra3_w_C3, "CPSSRA3_W_C3", MEPCOP1_32_INSN_CPSSRA3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cdsra3_C3, "CDSRA3_C3", MEPCOP1_32_INSN_CDSRA3_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpsll3_b_C3, "CPSLL3_B_C3", MEPCOP1_32_INSN_CPSLL3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpssll3_b_C3, "CPSSLL3_B_C3", MEPCOP1_32_INSN_CPSSLL3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpsll3_h_C3, "CPSLL3_H_C3", MEPCOP1_32_INSN_CPSLL3_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpssll3_h_C3, "CPSSLL3_H_C3", MEPCOP1_32_INSN_CPSSLL3_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpsll3_w_C3, "CPSLL3_W_C3", MEPCOP1_32_INSN_CPSLL3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpssll3_w_C3, "CPSSLL3_W_C3", MEPCOP1_32_INSN_CPSSLL3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cdsll3_C3, "CDSLL3_C3", MEPCOP1_32_INSN_CDSLL3_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpsla3_h_C3, "CPSLA3_H_C3", MEPCOP1_32_INSN_CPSLA3_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpsla3_w_C3, "CPSLA3_W_C3", MEPCOP1_32_INSN_CPSLA3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpsadd3_h_C3, "CPSADD3_H_C3", MEPCOP1_32_INSN_CPSADD3_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpsadd3_w_C3, "CPSADD3_W_C3", MEPCOP1_32_INSN_CPSADD3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpssub3_h_C3, "CPSSUB3_H_C3", MEPCOP1_32_INSN_CPSSUB3_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpssub3_w_C3, "CPSSUB3_W_C3", MEPCOP1_32_INSN_CPSSUB3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpextuaddu3_b_C3, "CPEXTUADDU3_B_C3", MEPCOP1_32_INSN_CPEXTUADDU3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpextuadd3_b_C3, "CPEXTUADD3_B_C3", MEPCOP1_32_INSN_CPEXTUADD3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpextladdu3_b_C3, "CPEXTLADDU3_B_C3", MEPCOP1_32_INSN_CPEXTLADDU3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpextladd3_b_C3, "CPEXTLADD3_B_C3", MEPCOP1_32_INSN_CPEXTLADD3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpextusubu3_b_C3, "CPEXTUSUBU3_B_C3", MEPCOP1_32_INSN_CPEXTUSUBU3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpextusub3_b_C3, "CPEXTUSUB3_B_C3", MEPCOP1_32_INSN_CPEXTUSUB3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpextlsubu3_b_C3, "CPEXTLSUBU3_B_C3", MEPCOP1_32_INSN_CPEXTLSUBU3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpextlsub3_b_C3, "CPEXTLSUB3_B_C3", MEPCOP1_32_INSN_CPEXTLSUB3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpaveu3_b_C3, "CPAVEU3_B_C3", MEPCOP1_32_INSN_CPAVEU3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpave3_b_C3, "CPAVE3_B_C3", MEPCOP1_32_INSN_CPAVE3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpave3_h_C3, "CPAVE3_H_C3", MEPCOP1_32_INSN_CPAVE3_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpave3_w_C3, "CPAVE3_W_C3", MEPCOP1_32_INSN_CPAVE3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpaddsru3_b_C3, "CPADDSRU3_B_C3", MEPCOP1_32_INSN_CPADDSRU3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpaddsr3_b_C3, "CPADDSR3_B_C3", MEPCOP1_32_INSN_CPADDSR3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpaddsr3_h_C3, "CPADDSR3_H_C3", MEPCOP1_32_INSN_CPADDSR3_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpaddsr3_w_C3, "CPADDSR3_W_C3", MEPCOP1_32_INSN_CPADDSR3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpabsu3_b_C3, "CPABSU3_B_C3", MEPCOP1_32_INSN_CPABSU3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpabs3_b_C3, "CPABS3_B_C3", MEPCOP1_32_INSN_CPABS3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpabs3_h_C3, "CPABS3_H_C3", MEPCOP1_32_INSN_CPABS3_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpmaxu3_b_C3, "CPMAXU3_B_C3", MEPCOP1_32_INSN_CPMAXU3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpmax3_b_C3, "CPMAX3_B_C3", MEPCOP1_32_INSN_CPMAX3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpmax3_h_C3, "CPMAX3_H_C3", MEPCOP1_32_INSN_CPMAX3_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpmaxu3_w_C3, "CPMAXU3_W_C3", MEPCOP1_32_INSN_CPMAXU3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpmax3_w_C3, "CPMAX3_W_C3", MEPCOP1_32_INSN_CPMAX3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpminu3_b_C3, "CPMINU3_B_C3", MEPCOP1_32_INSN_CPMINU3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpmin3_b_C3, "CPMIN3_B_C3", MEPCOP1_32_INSN_CPMIN3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpmin3_h_C3, "CPMIN3_H_C3", MEPCOP1_32_INSN_CPMIN3_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpminu3_w_C3, "CPMINU3_W_C3", MEPCOP1_32_INSN_CPMINU3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpmin3_w_C3, "CPMIN3_W_C3", MEPCOP1_32_INSN_CPMIN3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpmovfrcsar0_C3, "CPMOVFRCSAR0_C3", MEPCOP1_32_INSN_CPMOVFRCSAR0_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpmovfrcsar1_C3, "CPMOVFRCSAR1_C3", MEPCOP1_32_INSN_CPMOVFRCSAR1_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpmovfrcc_C3, "CPMOVFRCC_C3", MEPCOP1_32_INSN_CPMOVFRCC_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpmovtocsar0_C3, "CPMOVTOCSAR0_C3", MEPCOP1_32_INSN_CPMOVTOCSAR0_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpmovtocsar1_C3, "CPMOVTOCSAR1_C3", MEPCOP1_32_INSN_CPMOVTOCSAR1_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpmovtocc_C3, "CPMOVTOCC_C3", MEPCOP1_32_INSN_CPMOVTOCC_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpmov_C3, "CPMOV_C3", MEPCOP1_32_INSN_CPMOV_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpabsz_b_C3, "CPABSZ_B_C3", MEPCOP1_32_INSN_CPABSZ_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpabsz_h_C3, "CPABSZ_H_C3", MEPCOP1_32_INSN_CPABSZ_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpabsz_w_C3, "CPABSZ_W_C3", MEPCOP1_32_INSN_CPABSZ_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpldz_h_C3, "CPLDZ_H_C3", MEPCOP1_32_INSN_CPLDZ_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpldz_w_C3, "CPLDZ_W_C3", MEPCOP1_32_INSN_CPLDZ_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpnorm_h_C3, "CPNORM_H_C3", MEPCOP1_32_INSN_CPNORM_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpnorm_w_C3, "CPNORM_W_C3", MEPCOP1_32_INSN_CPNORM_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cphaddu_b_C3, "CPHADDU_B_C3", MEPCOP1_32_INSN_CPHADDU_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cphadd_b_C3, "CPHADD_B_C3", MEPCOP1_32_INSN_CPHADD_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cphadd_h_C3, "CPHADD_H_C3", MEPCOP1_32_INSN_CPHADD_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cphadd_w_C3, "CPHADD_W_C3", MEPCOP1_32_INSN_CPHADD_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpccadd_b_C3, "CPCCADD_B_C3", MEPCOP1_32_INSN_CPCCADD_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpbcast_b_C3, "CPBCAST_B_C3", MEPCOP1_32_INSN_CPBCAST_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpbcast_h_C3, "CPBCAST_H_C3", MEPCOP1_32_INSN_CPBCAST_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpbcast_w_C3, "CPBCAST_W_C3", MEPCOP1_32_INSN_CPBCAST_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpextuu_b_C3, "CPEXTUU_B_C3", MEPCOP1_32_INSN_CPEXTUU_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpextu_b_C3, "CPEXTU_B_C3", MEPCOP1_32_INSN_CPEXTU_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpextuu_h_C3, "CPEXTUU_H_C3", MEPCOP1_32_INSN_CPEXTUU_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpextu_h_C3, "CPEXTU_H_C3", MEPCOP1_32_INSN_CPEXTU_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpextlu_b_C3, "CPEXTLU_B_C3", MEPCOP1_32_INSN_CPEXTLU_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpextl_b_C3, "CPEXTL_B_C3", MEPCOP1_32_INSN_CPEXTL_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpextlu_h_C3, "CPEXTLU_H_C3", MEPCOP1_32_INSN_CPEXTLU_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpextl_h_C3, "CPEXTL_H_C3", MEPCOP1_32_INSN_CPEXTL_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpcastub_h_C3, "CPCASTUB_H_C3", MEPCOP1_32_INSN_CPCASTUB_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpcastb_h_C3, "CPCASTB_H_C3", MEPCOP1_32_INSN_CPCASTB_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpcastub_w_C3, "CPCASTUB_W_C3", MEPCOP1_32_INSN_CPCASTUB_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpcastb_w_C3, "CPCASTB_W_C3", MEPCOP1_32_INSN_CPCASTB_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpcastuh_w_C3, "CPCASTUH_W_C3", MEPCOP1_32_INSN_CPCASTUH_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpcasth_w_C3, "CPCASTH_W_C3", MEPCOP1_32_INSN_CPCASTH_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cdcastuw_C3, "CDCASTUW_C3", MEPCOP1_32_INSN_CDCASTUW_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cdcastw_C3, "CDCASTW_C3", MEPCOP1_32_INSN_CDCASTW_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpcmpeqz_b_C3, "CPCMPEQZ_B_C3", MEPCOP1_32_INSN_CPCMPEQZ_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpcmpeq_b_C3, "CPCMPEQ_B_C3", MEPCOP1_32_INSN_CPCMPEQ_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpcmpeq_h_C3, "CPCMPEQ_H_C3", MEPCOP1_32_INSN_CPCMPEQ_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpcmpeq_w_C3, "CPCMPEQ_W_C3", MEPCOP1_32_INSN_CPCMPEQ_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpcmpne_b_C3, "CPCMPNE_B_C3", MEPCOP1_32_INSN_CPCMPNE_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpcmpne_h_C3, "CPCMPNE_H_C3", MEPCOP1_32_INSN_CPCMPNE_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpcmpne_w_C3, "CPCMPNE_W_C3", MEPCOP1_32_INSN_CPCMPNE_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpcmpgtu_b_C3, "CPCMPGTU_B_C3", MEPCOP1_32_INSN_CPCMPGTU_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpcmpgt_b_C3, "CPCMPGT_B_C3", MEPCOP1_32_INSN_CPCMPGT_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpcmpgt_h_C3, "CPCMPGT_H_C3", MEPCOP1_32_INSN_CPCMPGT_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpcmpgtu_w_C3, "CPCMPGTU_W_C3", MEPCOP1_32_INSN_CPCMPGTU_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpcmpgt_w_C3, "CPCMPGT_W_C3", MEPCOP1_32_INSN_CPCMPGT_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpcmpgeu_b_C3, "CPCMPGEU_B_C3", MEPCOP1_32_INSN_CPCMPGEU_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpcmpge_b_C3, "CPCMPGE_B_C3", MEPCOP1_32_INSN_CPCMPGE_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpcmpge_h_C3, "CPCMPGE_H_C3", MEPCOP1_32_INSN_CPCMPGE_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpcmpgeu_w_C3, "CPCMPGEU_W_C3", MEPCOP1_32_INSN_CPCMPGEU_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpcmpge_w_C3, "CPCMPGE_W_C3", MEPCOP1_32_INSN_CPCMPGE_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpacmpeq_b_C3, "CPACMPEQ_B_C3", MEPCOP1_32_INSN_CPACMPEQ_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpacmpeq_h_C3, "CPACMPEQ_H_C3", MEPCOP1_32_INSN_CPACMPEQ_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpacmpeq_w_C3, "CPACMPEQ_W_C3", MEPCOP1_32_INSN_CPACMPEQ_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpacmpne_b_C3, "CPACMPNE_B_C3", MEPCOP1_32_INSN_CPACMPNE_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpacmpne_h_C3, "CPACMPNE_H_C3", MEPCOP1_32_INSN_CPACMPNE_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpacmpne_w_C3, "CPACMPNE_W_C3", MEPCOP1_32_INSN_CPACMPNE_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpacmpgtu_b_C3, "CPACMPGTU_B_C3", MEPCOP1_32_INSN_CPACMPGTU_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpacmpgt_b_C3, "CPACMPGT_B_C3", MEPCOP1_32_INSN_CPACMPGT_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpacmpgt_h_C3, "CPACMPGT_H_C3", MEPCOP1_32_INSN_CPACMPGT_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpacmpgtu_w_C3, "CPACMPGTU_W_C3", MEPCOP1_32_INSN_CPACMPGTU_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpacmpgt_w_C3, "CPACMPGT_W_C3", MEPCOP1_32_INSN_CPACMPGT_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpacmpgeu_b_C3, "CPACMPGEU_B_C3", MEPCOP1_32_INSN_CPACMPGEU_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpacmpge_b_C3, "CPACMPGE_B_C3", MEPCOP1_32_INSN_CPACMPGE_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpacmpge_h_C3, "CPACMPGE_H_C3", MEPCOP1_32_INSN_CPACMPGE_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpacmpgeu_w_C3, "CPACMPGEU_W_C3", MEPCOP1_32_INSN_CPACMPGEU_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpacmpge_w_C3, "CPACMPGE_W_C3", MEPCOP1_32_INSN_CPACMPGE_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpocmpeq_b_C3, "CPOCMPEQ_B_C3", MEPCOP1_32_INSN_CPOCMPEQ_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpocmpeq_h_C3, "CPOCMPEQ_H_C3", MEPCOP1_32_INSN_CPOCMPEQ_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpocmpeq_w_C3, "CPOCMPEQ_W_C3", MEPCOP1_32_INSN_CPOCMPEQ_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpocmpne_b_C3, "CPOCMPNE_B_C3", MEPCOP1_32_INSN_CPOCMPNE_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpocmpne_h_C3, "CPOCMPNE_H_C3", MEPCOP1_32_INSN_CPOCMPNE_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpocmpne_w_C3, "CPOCMPNE_W_C3", MEPCOP1_32_INSN_CPOCMPNE_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpocmpgtu_b_C3, "CPOCMPGTU_B_C3", MEPCOP1_32_INSN_CPOCMPGTU_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpocmpgt_b_C3, "CPOCMPGT_B_C3", MEPCOP1_32_INSN_CPOCMPGT_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpocmpgt_h_C3, "CPOCMPGT_H_C3", MEPCOP1_32_INSN_CPOCMPGT_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpocmpgtu_w_C3, "CPOCMPGTU_W_C3", MEPCOP1_32_INSN_CPOCMPGTU_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpocmpgt_w_C3, "CPOCMPGT_W_C3", MEPCOP1_32_INSN_CPOCMPGT_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpocmpgeu_b_C3, "CPOCMPGEU_B_C3", MEPCOP1_32_INSN_CPOCMPGEU_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpocmpge_b_C3, "CPOCMPGE_B_C3", MEPCOP1_32_INSN_CPOCMPGE_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpocmpge_h_C3, "CPOCMPGE_H_C3", MEPCOP1_32_INSN_CPOCMPGE_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpocmpgeu_w_C3, "CPOCMPGEU_W_C3", MEPCOP1_32_INSN_CPOCMPGEU_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpocmpge_w_C3, "CPOCMPGE_W_C3", MEPCOP1_32_INSN_CPOCMPGE_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpsrli3_b_C3, "CPSRLI3_B_C3", MEPCOP1_32_INSN_CPSRLI3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpsrli3_h_C3, "CPSRLI3_H_C3", MEPCOP1_32_INSN_CPSRLI3_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpsrli3_w_C3, "CPSRLI3_W_C3", MEPCOP1_32_INSN_CPSRLI3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cdsrli3_C3, "CDSRLI3_C3", MEPCOP1_32_INSN_CDSRLI3_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpsrai3_b_C3, "CPSRAI3_B_C3", MEPCOP1_32_INSN_CPSRAI3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpsrai3_h_C3, "CPSRAI3_H_C3", MEPCOP1_32_INSN_CPSRAI3_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpsrai3_w_C3, "CPSRAI3_W_C3", MEPCOP1_32_INSN_CPSRAI3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cdsrai3_C3, "CDSRAI3_C3", MEPCOP1_32_INSN_CDSRAI3_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpslli3_b_C3, "CPSLLI3_B_C3", MEPCOP1_32_INSN_CPSLLI3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpslli3_h_C3, "CPSLLI3_H_C3", MEPCOP1_32_INSN_CPSLLI3_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpslli3_w_C3, "CPSLLI3_W_C3", MEPCOP1_32_INSN_CPSLLI3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cdslli3_C3, "CDSLLI3_C3", MEPCOP1_32_INSN_CDSLLI3_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpslai3_h_C3, "CPSLAI3_H_C3", MEPCOP1_32_INSN_CPSLAI3_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpslai3_w_C3, "CPSLAI3_W_C3", MEPCOP1_32_INSN_CPSLAI3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpclipiu3_w_C3, "CPCLIPIU3_W_C3", MEPCOP1_32_INSN_CPCLIPIU3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpclipi3_w_C3, "CPCLIPI3_W_C3", MEPCOP1_32_INSN_CPCLIPI3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cdclipiu3_C3, "CDCLIPIU3_C3", MEPCOP1_32_INSN_CDCLIPIU3_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cdclipi3_C3, "CDCLIPI3_C3", MEPCOP1_32_INSN_CDCLIPI3_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpmovi_b_C3, "CPMOVI_B_C3", MEPCOP1_32_INSN_CPMOVI_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpmoviu_h_C3, "CPMOVIU_H_C3", MEPCOP1_32_INSN_CPMOVIU_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpmovi_h_C3, "CPMOVI_H_C3", MEPCOP1_32_INSN_CPMOVI_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpmoviu_w_C3, "CPMOVIU_W_C3", MEPCOP1_32_INSN_CPMOVIU_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpmovi_w_C3, "CPMOVI_W_C3", MEPCOP1_32_INSN_CPMOVI_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cdmoviu_C3, "CDMOVIU_C3", MEPCOP1_32_INSN_CDMOVIU_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cdmovi_C3, "CDMOVI_C3", MEPCOP1_32_INSN_CDMOVI_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpadda1u_b_C3, "CPADDA1U_B_C3", MEPCOP1_32_INSN_CPADDA1U_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpadda1_b_C3, "CPADDA1_B_C3", MEPCOP1_32_INSN_CPADDA1_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpaddua1_h_C3, "CPADDUA1_H_C3", MEPCOP1_32_INSN_CPADDUA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpaddla1_h_C3, "CPADDLA1_H_C3", MEPCOP1_32_INSN_CPADDLA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpaddaca1u_b_C3, "CPADDACA1U_B_C3", MEPCOP1_32_INSN_CPADDACA1U_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpaddaca1_b_C3, "CPADDACA1_B_C3", MEPCOP1_32_INSN_CPADDACA1_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpaddacua1_h_C3, "CPADDACUA1_H_C3", MEPCOP1_32_INSN_CPADDACUA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpaddacla1_h_C3, "CPADDACLA1_H_C3", MEPCOP1_32_INSN_CPADDACLA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpsuba1u_b_C3, "CPSUBA1U_B_C3", MEPCOP1_32_INSN_CPSUBA1U_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpsuba1_b_C3, "CPSUBA1_B_C3", MEPCOP1_32_INSN_CPSUBA1_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpsubua1_h_C3, "CPSUBUA1_H_C3", MEPCOP1_32_INSN_CPSUBUA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpsubla1_h_C3, "CPSUBLA1_H_C3", MEPCOP1_32_INSN_CPSUBLA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpsubaca1u_b_C3, "CPSUBACA1U_B_C3", MEPCOP1_32_INSN_CPSUBACA1U_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpsubaca1_b_C3, "CPSUBACA1_B_C3", MEPCOP1_32_INSN_CPSUBACA1_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpsubacua1_h_C3, "CPSUBACUA1_H_C3", MEPCOP1_32_INSN_CPSUBACUA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpsubacla1_h_C3, "CPSUBACLA1_H_C3", MEPCOP1_32_INSN_CPSUBACLA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpabsa1u_b_C3, "CPABSA1U_B_C3", MEPCOP1_32_INSN_CPABSA1U_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpabsa1_b_C3, "CPABSA1_B_C3", MEPCOP1_32_INSN_CPABSA1_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpabsua1_h_C3, "CPABSUA1_H_C3", MEPCOP1_32_INSN_CPABSUA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpabsla1_h_C3, "CPABSLA1_H_C3", MEPCOP1_32_INSN_CPABSLA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpsada1u_b_C3, "CPSADA1U_B_C3", MEPCOP1_32_INSN_CPSADA1U_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpsada1_b_C3, "CPSADA1_B_C3", MEPCOP1_32_INSN_CPSADA1_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpsadua1_h_C3, "CPSADUA1_H_C3", MEPCOP1_32_INSN_CPSADUA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpsadla1_h_C3, "CPSADLA1_H_C3", MEPCOP1_32_INSN_CPSADLA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpseta1_h_C3, "CPSETA1_H_C3", MEPCOP1_32_INSN_CPSETA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpsetua1_w_C3, "CPSETUA1_W_C3", MEPCOP1_32_INSN_CPSETUA1_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpsetla1_w_C3, "CPSETLA1_W_C3", MEPCOP1_32_INSN_CPSETLA1_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpmova1_b_C3, "CPMOVA1_B_C3", MEPCOP1_32_INSN_CPMOVA1_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpmovua1_h_C3, "CPMOVUA1_H_C3", MEPCOP1_32_INSN_CPMOVUA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpmovla1_h_C3, "CPMOVLA1_H_C3", MEPCOP1_32_INSN_CPMOVLA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpmovuua1_w_C3, "CPMOVUUA1_W_C3", MEPCOP1_32_INSN_CPMOVUUA1_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpmovula1_w_C3, "CPMOVULA1_W_C3", MEPCOP1_32_INSN_CPMOVULA1_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpmovlua1_w_C3, "CPMOVLUA1_W_C3", MEPCOP1_32_INSN_CPMOVLUA1_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpmovlla1_w_C3, "CPMOVLLA1_W_C3", MEPCOP1_32_INSN_CPMOVLLA1_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cppacka1u_b_C3, "CPPACKA1U_B_C3", MEPCOP1_32_INSN_CPPACKA1U_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cppacka1_b_C3, "CPPACKA1_B_C3", MEPCOP1_32_INSN_CPPACKA1_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cppackua1_h_C3, "CPPACKUA1_H_C3", MEPCOP1_32_INSN_CPPACKUA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cppackla1_h_C3, "CPPACKLA1_H_C3", MEPCOP1_32_INSN_CPPACKLA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cppackua1_w_C3, "CPPACKUA1_W_C3", MEPCOP1_32_INSN_CPPACKUA1_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cppackla1_w_C3, "CPPACKLA1_W_C3", MEPCOP1_32_INSN_CPPACKLA1_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpmovhua1_w_C3, "CPMOVHUA1_W_C3", MEPCOP1_32_INSN_CPMOVHUA1_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpmovhla1_w_C3, "CPMOVHLA1_W_C3", MEPCOP1_32_INSN_CPMOVHLA1_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpsrla1_C3, "CPSRLA1_C3", MEPCOP1_32_INSN_CPSRLA1_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpsraa1_C3, "CPSRAA1_C3", MEPCOP1_32_INSN_CPSRAA1_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpslla1_C3, "CPSLLA1_C3", MEPCOP1_32_INSN_CPSLLA1_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpsrlia1_P1, "CPSRLIA1_P1", MEPCOP1_32_INSN_CPSRLIA1_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpsraia1_P1, "CPSRAIA1_P1", MEPCOP1_32_INSN_CPSRAIA1_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpsllia1_P1, "CPSLLIA1_P1", MEPCOP1_32_INSN_CPSLLIA1_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpssqa1u_b_C3, "CPSSQA1U_B_C3", MEPCOP1_32_INSN_CPSSQA1U_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpssqa1_b_C3, "CPSSQA1_B_C3", MEPCOP1_32_INSN_CPSSQA1_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpssda1u_b_C3, "CPSSDA1U_B_C3", MEPCOP1_32_INSN_CPSSDA1U_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpssda1_b_C3, "CPSSDA1_B_C3", MEPCOP1_32_INSN_CPSSDA1_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpmula1u_b_C3, "CPMULA1U_B_C3", MEPCOP1_32_INSN_CPMULA1U_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpmula1_b_C3, "CPMULA1_B_C3", MEPCOP1_32_INSN_CPMULA1_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpmulua1_h_C3, "CPMULUA1_H_C3", MEPCOP1_32_INSN_CPMULUA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpmulla1_h_C3, "CPMULLA1_H_C3", MEPCOP1_32_INSN_CPMULLA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpmulua1u_w_C3, "CPMULUA1U_W_C3", MEPCOP1_32_INSN_CPMULUA1U_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpmulla1u_w_C3, "CPMULLA1U_W_C3", MEPCOP1_32_INSN_CPMULLA1U_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpmulua1_w_C3, "CPMULUA1_W_C3", MEPCOP1_32_INSN_CPMULUA1_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpmulla1_w_C3, "CPMULLA1_W_C3", MEPCOP1_32_INSN_CPMULLA1_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpmada1u_b_C3, "CPMADA1U_B_C3", MEPCOP1_32_INSN_CPMADA1U_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpmada1_b_C3, "CPMADA1_B_C3", MEPCOP1_32_INSN_CPMADA1_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpmadua1_h_C3, "CPMADUA1_H_C3", MEPCOP1_32_INSN_CPMADUA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpmadla1_h_C3, "CPMADLA1_H_C3", MEPCOP1_32_INSN_CPMADLA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpmadua1u_w_C3, "CPMADUA1U_W_C3", MEPCOP1_32_INSN_CPMADUA1U_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpmadla1u_w_C3, "CPMADLA1U_W_C3", MEPCOP1_32_INSN_CPMADLA1U_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpmadua1_w_C3, "CPMADUA1_W_C3", MEPCOP1_32_INSN_CPMADUA1_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpmadla1_w_C3, "CPMADLA1_W_C3", MEPCOP1_32_INSN_CPMADLA1_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpmsbua1_h_C3, "CPMSBUA1_H_C3", MEPCOP1_32_INSN_CPMSBUA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpmsbla1_h_C3, "CPMSBLA1_H_C3", MEPCOP1_32_INSN_CPMSBLA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpmsbua1u_w_C3, "CPMSBUA1U_W_C3", MEPCOP1_32_INSN_CPMSBUA1U_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpmsbla1u_w_C3, "CPMSBLA1U_W_C3", MEPCOP1_32_INSN_CPMSBLA1U_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpmsbua1_w_C3, "CPMSBUA1_W_C3", MEPCOP1_32_INSN_CPMSBUA1_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpmsbla1_w_C3, "CPMSBLA1_W_C3", MEPCOP1_32_INSN_CPMSBLA1_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpsmadua1_h_C3, "CPSMADUA1_H_C3", MEPCOP1_32_INSN_CPSMADUA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpsmadla1_h_C3, "CPSMADLA1_H_C3", MEPCOP1_32_INSN_CPSMADLA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpsmadua1_w_C3, "CPSMADUA1_W_C3", MEPCOP1_32_INSN_CPSMADUA1_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpsmadla1_w_C3, "CPSMADLA1_W_C3", MEPCOP1_32_INSN_CPSMADLA1_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpsmsbua1_h_C3, "CPSMSBUA1_H_C3", MEPCOP1_32_INSN_CPSMSBUA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpsmsbla1_h_C3, "CPSMSBLA1_H_C3", MEPCOP1_32_INSN_CPSMSBLA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpsmsbua1_w_C3, "CPSMSBUA1_W_C3", MEPCOP1_32_INSN_CPSMSBUA1_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpsmsbla1_w_C3, "CPSMSBLA1_W_C3", MEPCOP1_32_INSN_CPSMSBLA1_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpmulslua1_h_C3, "CPMULSLUA1_H_C3", MEPCOP1_32_INSN_CPMULSLUA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpmulslla1_h_C3, "CPMULSLLA1_H_C3", MEPCOP1_32_INSN_CPMULSLLA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpmulslua1_w_C3, "CPMULSLUA1_W_C3", MEPCOP1_32_INSN_CPMULSLUA1_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpmulslla1_w_C3, "CPMULSLLA1_W_C3", MEPCOP1_32_INSN_CPMULSLLA1_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpsmadslua1_h_C3, "CPSMADSLUA1_H_C3", MEPCOP1_32_INSN_CPSMADSLUA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpsmadslla1_h_C3, "CPSMADSLLA1_H_C3", MEPCOP1_32_INSN_CPSMADSLLA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpsmadslua1_w_C3, "CPSMADSLUA1_W_C3", MEPCOP1_32_INSN_CPSMADSLUA1_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpsmadslla1_w_C3, "CPSMADSLLA1_W_C3", MEPCOP1_32_INSN_CPSMADSLLA1_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpsmsbslua1_h_C3, "CPSMSBSLUA1_H_C3", MEPCOP1_32_INSN_CPSMSBSLUA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpsmsbslla1_h_C3, "CPSMSBSLLA1_H_C3", MEPCOP1_32_INSN_CPSMSBSLLA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpsmsbslua1_w_C3, "CPSMSBSLUA1_W_C3", MEPCOP1_32_INSN_CPSMSBSLUA1_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
-  { mepcop1_32_sem_cpsmsbslla1_w_C3, "CPSMSBSLLA1_W_C3", MEPCOP1_32_INSN_CPSMSBSLLA1_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_x_invalid, "X_INVALID", MEPCOP1_32_INSN_X_INVALID, { 0|(1<<CGEN_INSN_VIRTUAL), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+  { mepcop1_32_sem_cmov_crn_rm, "CMOV_CRN_RM", MEPCOP1_32_INSN_CMOV_CRN_RM, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cmov_rn_crm, "CMOV_RN_CRM", MEPCOP1_32_INSN_CMOV_RN_CRM, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cmovc_ccrn_rm, "CMOVC_CCRN_RM", MEPCOP1_32_INSN_CMOVC_CCRN_RM, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cmovc_rn_ccrm, "CMOVC_RN_CCRM", MEPCOP1_32_INSN_CMOVC_RN_CCRM, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cmovh_crn_rm, "CMOVH_CRN_RM", MEPCOP1_32_INSN_CMOVH_CRN_RM, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cmovh_rn_crm, "CMOVH_RN_CRM", MEPCOP1_32_INSN_CMOVH_RN_CRM, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpadd3_b_C3, "CPADD3_B_C3", MEPCOP1_32_INSN_CPADD3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpadd3_h_C3, "CPADD3_H_C3", MEPCOP1_32_INSN_CPADD3_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpadd3_w_C3, "CPADD3_W_C3", MEPCOP1_32_INSN_CPADD3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cdadd3_C3, "CDADD3_C3", MEPCOP1_32_INSN_CDADD3_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpsub3_b_C3, "CPSUB3_B_C3", MEPCOP1_32_INSN_CPSUB3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpsub3_h_C3, "CPSUB3_H_C3", MEPCOP1_32_INSN_CPSUB3_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpsub3_w_C3, "CPSUB3_W_C3", MEPCOP1_32_INSN_CPSUB3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cdsub3_C3, "CDSUB3_C3", MEPCOP1_32_INSN_CDSUB3_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpand3_C3, "CPAND3_C3", MEPCOP1_32_INSN_CPAND3_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_VECT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpor3_C3, "CPOR3_C3", MEPCOP1_32_INSN_CPOR3_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_VECT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpnor3_C3, "CPNOR3_C3", MEPCOP1_32_INSN_CPNOR3_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_VECT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpxor3_C3, "CPXOR3_C3", MEPCOP1_32_INSN_CPXOR3_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_VECT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpsel_C3, "CPSEL_C3", MEPCOP1_32_INSN_CPSEL_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpfsftbi_C3, "CPFSFTBI_C3", MEPCOP1_32_INSN_CPFSFTBI_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpfsftbs0_C3, "CPFSFTBS0_C3", MEPCOP1_32_INSN_CPFSFTBS0_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpfsftbs1_C3, "CPFSFTBS1_C3", MEPCOP1_32_INSN_CPFSFTBS1_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpunpacku_b_C3, "CPUNPACKU_B_C3", MEPCOP1_32_INSN_CPUNPACKU_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8UQI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpunpacku_h_C3, "CPUNPACKU_H_C3", MEPCOP1_32_INSN_CPUNPACKU_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4UHI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpunpacku_w_C3, "CPUNPACKU_W_C3", MEPCOP1_32_INSN_CPUNPACKU_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2USI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpunpackl_b_C3, "CPUNPACKL_B_C3", MEPCOP1_32_INSN_CPUNPACKL_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpunpackl_h_C3, "CPUNPACKL_H_C3", MEPCOP1_32_INSN_CPUNPACKL_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpunpackl_w_C3, "CPUNPACKL_W_C3", MEPCOP1_32_INSN_CPUNPACKL_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cppacku_b_C3, "CPPACKU_B_C3", MEPCOP1_32_INSN_CPPACKU_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8UQI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cppack_b_C3, "CPPACK_B_C3", MEPCOP1_32_INSN_CPPACK_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cppack_h_C3, "CPPACK_H_C3", MEPCOP1_32_INSN_CPPACK_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpsrl3_b_C3, "CPSRL3_B_C3", MEPCOP1_32_INSN_CPSRL3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpssrl3_b_C3, "CPSSRL3_B_C3", MEPCOP1_32_INSN_CPSSRL3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpsrl3_h_C3, "CPSRL3_H_C3", MEPCOP1_32_INSN_CPSRL3_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpssrl3_h_C3, "CPSSRL3_H_C3", MEPCOP1_32_INSN_CPSSRL3_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpsrl3_w_C3, "CPSRL3_W_C3", MEPCOP1_32_INSN_CPSRL3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpssrl3_w_C3, "CPSSRL3_W_C3", MEPCOP1_32_INSN_CPSSRL3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cdsrl3_C3, "CDSRL3_C3", MEPCOP1_32_INSN_CDSRL3_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpsra3_b_C3, "CPSRA3_B_C3", MEPCOP1_32_INSN_CPSRA3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpssra3_b_C3, "CPSSRA3_B_C3", MEPCOP1_32_INSN_CPSSRA3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpsra3_h_C3, "CPSRA3_H_C3", MEPCOP1_32_INSN_CPSRA3_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpssra3_h_C3, "CPSSRA3_H_C3", MEPCOP1_32_INSN_CPSSRA3_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpsra3_w_C3, "CPSRA3_W_C3", MEPCOP1_32_INSN_CPSRA3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpssra3_w_C3, "CPSSRA3_W_C3", MEPCOP1_32_INSN_CPSSRA3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cdsra3_C3, "CDSRA3_C3", MEPCOP1_32_INSN_CDSRA3_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpsll3_b_C3, "CPSLL3_B_C3", MEPCOP1_32_INSN_CPSLL3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpssll3_b_C3, "CPSSLL3_B_C3", MEPCOP1_32_INSN_CPSSLL3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpsll3_h_C3, "CPSLL3_H_C3", MEPCOP1_32_INSN_CPSLL3_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpssll3_h_C3, "CPSSLL3_H_C3", MEPCOP1_32_INSN_CPSSLL3_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpsll3_w_C3, "CPSLL3_W_C3", MEPCOP1_32_INSN_CPSLL3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpssll3_w_C3, "CPSSLL3_W_C3", MEPCOP1_32_INSN_CPSSLL3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cdsll3_C3, "CDSLL3_C3", MEPCOP1_32_INSN_CDSLL3_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpsla3_h_C3, "CPSLA3_H_C3", MEPCOP1_32_INSN_CPSLA3_H_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpsla3_w_C3, "CPSLA3_W_C3", MEPCOP1_32_INSN_CPSLA3_W_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpsadd3_h_C3, "CPSADD3_H_C3", MEPCOP1_32_INSN_CPSADD3_H_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpsadd3_w_C3, "CPSADD3_W_C3", MEPCOP1_32_INSN_CPSADD3_W_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpssub3_h_C3, "CPSSUB3_H_C3", MEPCOP1_32_INSN_CPSSUB3_H_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpssub3_w_C3, "CPSSUB3_W_C3", MEPCOP1_32_INSN_CPSSUB3_W_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpextuaddu3_b_C3, "CPEXTUADDU3_B_C3", MEPCOP1_32_INSN_CPEXTUADDU3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpextuadd3_b_C3, "CPEXTUADD3_B_C3", MEPCOP1_32_INSN_CPEXTUADD3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpextladdu3_b_C3, "CPEXTLADDU3_B_C3", MEPCOP1_32_INSN_CPEXTLADDU3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpextladd3_b_C3, "CPEXTLADD3_B_C3", MEPCOP1_32_INSN_CPEXTLADD3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpextusubu3_b_C3, "CPEXTUSUBU3_B_C3", MEPCOP1_32_INSN_CPEXTUSUBU3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpextusub3_b_C3, "CPEXTUSUB3_B_C3", MEPCOP1_32_INSN_CPEXTUSUB3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpextlsubu3_b_C3, "CPEXTLSUBU3_B_C3", MEPCOP1_32_INSN_CPEXTLSUBU3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpextlsub3_b_C3, "CPEXTLSUB3_B_C3", MEPCOP1_32_INSN_CPEXTLSUB3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpaveu3_b_C3, "CPAVEU3_B_C3", MEPCOP1_32_INSN_CPAVEU3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpave3_b_C3, "CPAVE3_B_C3", MEPCOP1_32_INSN_CPAVE3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpave3_h_C3, "CPAVE3_H_C3", MEPCOP1_32_INSN_CPAVE3_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpave3_w_C3, "CPAVE3_W_C3", MEPCOP1_32_INSN_CPAVE3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpaddsru3_b_C3, "CPADDSRU3_B_C3", MEPCOP1_32_INSN_CPADDSRU3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpaddsr3_b_C3, "CPADDSR3_B_C3", MEPCOP1_32_INSN_CPADDSR3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpaddsr3_h_C3, "CPADDSR3_H_C3", MEPCOP1_32_INSN_CPADDSR3_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpaddsr3_w_C3, "CPADDSR3_W_C3", MEPCOP1_32_INSN_CPADDSR3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpabsu3_b_C3, "CPABSU3_B_C3", MEPCOP1_32_INSN_CPABSU3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpabs3_b_C3, "CPABS3_B_C3", MEPCOP1_32_INSN_CPABS3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpabs3_h_C3, "CPABS3_H_C3", MEPCOP1_32_INSN_CPABS3_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpmaxu3_b_C3, "CPMAXU3_B_C3", MEPCOP1_32_INSN_CPMAXU3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpmax3_b_C3, "CPMAX3_B_C3", MEPCOP1_32_INSN_CPMAX3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpmax3_h_C3, "CPMAX3_H_C3", MEPCOP1_32_INSN_CPMAX3_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpmaxu3_w_C3, "CPMAXU3_W_C3", MEPCOP1_32_INSN_CPMAXU3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpmax3_w_C3, "CPMAX3_W_C3", MEPCOP1_32_INSN_CPMAX3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpminu3_b_C3, "CPMINU3_B_C3", MEPCOP1_32_INSN_CPMINU3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpmin3_b_C3, "CPMIN3_B_C3", MEPCOP1_32_INSN_CPMIN3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpmin3_h_C3, "CPMIN3_H_C3", MEPCOP1_32_INSN_CPMIN3_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpminu3_w_C3, "CPMINU3_W_C3", MEPCOP1_32_INSN_CPMINU3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpmin3_w_C3, "CPMIN3_W_C3", MEPCOP1_32_INSN_CPMIN3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpmovfrcsar0_C3, "CPMOVFRCSAR0_C3", MEPCOP1_32_INSN_CPMOVFRCSAR0_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpmovfrcsar1_C3, "CPMOVFRCSAR1_C3", MEPCOP1_32_INSN_CPMOVFRCSAR1_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpmovfrcc_C3, "CPMOVFRCC_C3", MEPCOP1_32_INSN_CPMOVFRCC_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpmovtocsar0_C3, "CPMOVTOCSAR0_C3", MEPCOP1_32_INSN_CPMOVTOCSAR0_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpmovtocsar1_C3, "CPMOVTOCSAR1_C3", MEPCOP1_32_INSN_CPMOVTOCSAR1_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpmovtocc_C3, "CPMOVTOCC_C3", MEPCOP1_32_INSN_CPMOVTOCC_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpmov_C3, "CPMOV_C3", MEPCOP1_32_INSN_CPMOV_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpabsz_b_C3, "CPABSZ_B_C3", MEPCOP1_32_INSN_CPABSZ_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpabsz_h_C3, "CPABSZ_H_C3", MEPCOP1_32_INSN_CPABSZ_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpabsz_w_C3, "CPABSZ_W_C3", MEPCOP1_32_INSN_CPABSZ_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpldz_h_C3, "CPLDZ_H_C3", MEPCOP1_32_INSN_CPLDZ_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpldz_w_C3, "CPLDZ_W_C3", MEPCOP1_32_INSN_CPLDZ_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpnorm_h_C3, "CPNORM_H_C3", MEPCOP1_32_INSN_CPNORM_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpnorm_w_C3, "CPNORM_W_C3", MEPCOP1_32_INSN_CPNORM_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cphaddu_b_C3, "CPHADDU_B_C3", MEPCOP1_32_INSN_CPHADDU_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8UQI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cphadd_b_C3, "CPHADD_B_C3", MEPCOP1_32_INSN_CPHADD_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cphadd_h_C3, "CPHADD_H_C3", MEPCOP1_32_INSN_CPHADD_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cphadd_w_C3, "CPHADD_W_C3", MEPCOP1_32_INSN_CPHADD_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpccadd_b_C3, "CPCCADD_B_C3", MEPCOP1_32_INSN_CPCCADD_B_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_FIRSTCOPY, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpbcast_b_C3, "CPBCAST_B_C3", MEPCOP1_32_INSN_CPBCAST_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpbcast_h_C3, "CPBCAST_H_C3", MEPCOP1_32_INSN_CPBCAST_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpbcast_w_C3, "CPBCAST_W_C3", MEPCOP1_32_INSN_CPBCAST_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpextuu_b_C3, "CPEXTUU_B_C3", MEPCOP1_32_INSN_CPEXTUU_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8UQI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpextu_b_C3, "CPEXTU_B_C3", MEPCOP1_32_INSN_CPEXTU_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8UQI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpextuu_h_C3, "CPEXTUU_H_C3", MEPCOP1_32_INSN_CPEXTUU_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4UHI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpextu_h_C3, "CPEXTU_H_C3", MEPCOP1_32_INSN_CPEXTU_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4UHI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpextlu_b_C3, "CPEXTLU_B_C3", MEPCOP1_32_INSN_CPEXTLU_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8UQI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpextl_b_C3, "CPEXTL_B_C3", MEPCOP1_32_INSN_CPEXTL_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpextlu_h_C3, "CPEXTLU_H_C3", MEPCOP1_32_INSN_CPEXTLU_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4UHI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpextl_h_C3, "CPEXTL_H_C3", MEPCOP1_32_INSN_CPEXTL_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpcastub_h_C3, "CPCASTUB_H_C3", MEPCOP1_32_INSN_CPCASTUB_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpcastb_h_C3, "CPCASTB_H_C3", MEPCOP1_32_INSN_CPCASTB_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpcastub_w_C3, "CPCASTUB_W_C3", MEPCOP1_32_INSN_CPCASTUB_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpcastb_w_C3, "CPCASTB_W_C3", MEPCOP1_32_INSN_CPCASTB_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpcastuh_w_C3, "CPCASTUH_W_C3", MEPCOP1_32_INSN_CPCASTUH_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpcasth_w_C3, "CPCASTH_W_C3", MEPCOP1_32_INSN_CPCASTH_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cdcastuw_C3, "CDCASTUW_C3", MEPCOP1_32_INSN_CDCASTUW_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cdcastw_C3, "CDCASTW_C3", MEPCOP1_32_INSN_CDCASTW_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpcmpeqz_b_C3, "CPCMPEQZ_B_C3", MEPCOP1_32_INSN_CPCMPEQZ_B_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpcmpeq_b_C3, "CPCMPEQ_B_C3", MEPCOP1_32_INSN_CPCMPEQ_B_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpcmpeq_h_C3, "CPCMPEQ_H_C3", MEPCOP1_32_INSN_CPCMPEQ_H_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpcmpeq_w_C3, "CPCMPEQ_W_C3", MEPCOP1_32_INSN_CPCMPEQ_W_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpcmpne_b_C3, "CPCMPNE_B_C3", MEPCOP1_32_INSN_CPCMPNE_B_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpcmpne_h_C3, "CPCMPNE_H_C3", MEPCOP1_32_INSN_CPCMPNE_H_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpcmpne_w_C3, "CPCMPNE_W_C3", MEPCOP1_32_INSN_CPCMPNE_W_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpcmpgtu_b_C3, "CPCMPGTU_B_C3", MEPCOP1_32_INSN_CPCMPGTU_B_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8UQI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpcmpgt_b_C3, "CPCMPGT_B_C3", MEPCOP1_32_INSN_CPCMPGT_B_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpcmpgt_h_C3, "CPCMPGT_H_C3", MEPCOP1_32_INSN_CPCMPGT_H_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpcmpgtu_w_C3, "CPCMPGTU_W_C3", MEPCOP1_32_INSN_CPCMPGTU_W_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2USI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpcmpgt_w_C3, "CPCMPGT_W_C3", MEPCOP1_32_INSN_CPCMPGT_W_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpcmpgeu_b_C3, "CPCMPGEU_B_C3", MEPCOP1_32_INSN_CPCMPGEU_B_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8UQI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpcmpge_b_C3, "CPCMPGE_B_C3", MEPCOP1_32_INSN_CPCMPGE_B_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpcmpge_h_C3, "CPCMPGE_H_C3", MEPCOP1_32_INSN_CPCMPGE_H_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpcmpgeu_w_C3, "CPCMPGEU_W_C3", MEPCOP1_32_INSN_CPCMPGEU_W_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2USI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpcmpge_w_C3, "CPCMPGE_W_C3", MEPCOP1_32_INSN_CPCMPGE_W_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpacmpeq_b_C3, "CPACMPEQ_B_C3", MEPCOP1_32_INSN_CPACMPEQ_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpacmpeq_h_C3, "CPACMPEQ_H_C3", MEPCOP1_32_INSN_CPACMPEQ_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpacmpeq_w_C3, "CPACMPEQ_W_C3", MEPCOP1_32_INSN_CPACMPEQ_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpacmpne_b_C3, "CPACMPNE_B_C3", MEPCOP1_32_INSN_CPACMPNE_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpacmpne_h_C3, "CPACMPNE_H_C3", MEPCOP1_32_INSN_CPACMPNE_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpacmpne_w_C3, "CPACMPNE_W_C3", MEPCOP1_32_INSN_CPACMPNE_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpacmpgtu_b_C3, "CPACMPGTU_B_C3", MEPCOP1_32_INSN_CPACMPGTU_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8UQI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpacmpgt_b_C3, "CPACMPGT_B_C3", MEPCOP1_32_INSN_CPACMPGT_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpacmpgt_h_C3, "CPACMPGT_H_C3", MEPCOP1_32_INSN_CPACMPGT_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpacmpgtu_w_C3, "CPACMPGTU_W_C3", MEPCOP1_32_INSN_CPACMPGTU_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2USI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpacmpgt_w_C3, "CPACMPGT_W_C3", MEPCOP1_32_INSN_CPACMPGT_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpacmpgeu_b_C3, "CPACMPGEU_B_C3", MEPCOP1_32_INSN_CPACMPGEU_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8UQI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpacmpge_b_C3, "CPACMPGE_B_C3", MEPCOP1_32_INSN_CPACMPGE_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpacmpge_h_C3, "CPACMPGE_H_C3", MEPCOP1_32_INSN_CPACMPGE_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpacmpgeu_w_C3, "CPACMPGEU_W_C3", MEPCOP1_32_INSN_CPACMPGEU_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2USI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpacmpge_w_C3, "CPACMPGE_W_C3", MEPCOP1_32_INSN_CPACMPGE_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpocmpeq_b_C3, "CPOCMPEQ_B_C3", MEPCOP1_32_INSN_CPOCMPEQ_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpocmpeq_h_C3, "CPOCMPEQ_H_C3", MEPCOP1_32_INSN_CPOCMPEQ_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpocmpeq_w_C3, "CPOCMPEQ_W_C3", MEPCOP1_32_INSN_CPOCMPEQ_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpocmpne_b_C3, "CPOCMPNE_B_C3", MEPCOP1_32_INSN_CPOCMPNE_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpocmpne_h_C3, "CPOCMPNE_H_C3", MEPCOP1_32_INSN_CPOCMPNE_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpocmpne_w_C3, "CPOCMPNE_W_C3", MEPCOP1_32_INSN_CPOCMPNE_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpocmpgtu_b_C3, "CPOCMPGTU_B_C3", MEPCOP1_32_INSN_CPOCMPGTU_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8UQI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpocmpgt_b_C3, "CPOCMPGT_B_C3", MEPCOP1_32_INSN_CPOCMPGT_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpocmpgt_h_C3, "CPOCMPGT_H_C3", MEPCOP1_32_INSN_CPOCMPGT_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpocmpgtu_w_C3, "CPOCMPGTU_W_C3", MEPCOP1_32_INSN_CPOCMPGTU_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2USI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpocmpgt_w_C3, "CPOCMPGT_W_C3", MEPCOP1_32_INSN_CPOCMPGT_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpocmpgeu_b_C3, "CPOCMPGEU_B_C3", MEPCOP1_32_INSN_CPOCMPGEU_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8UQI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpocmpge_b_C3, "CPOCMPGE_B_C3", MEPCOP1_32_INSN_CPOCMPGE_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpocmpge_h_C3, "CPOCMPGE_H_C3", MEPCOP1_32_INSN_CPOCMPGE_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpocmpgeu_w_C3, "CPOCMPGEU_W_C3", MEPCOP1_32_INSN_CPOCMPGEU_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2USI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpocmpge_w_C3, "CPOCMPGE_W_C3", MEPCOP1_32_INSN_CPOCMPGE_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpsrli3_b_C3, "CPSRLI3_B_C3", MEPCOP1_32_INSN_CPSRLI3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpsrli3_h_C3, "CPSRLI3_H_C3", MEPCOP1_32_INSN_CPSRLI3_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpsrli3_w_C3, "CPSRLI3_W_C3", MEPCOP1_32_INSN_CPSRLI3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cdsrli3_C3, "CDSRLI3_C3", MEPCOP1_32_INSN_CDSRLI3_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpsrai3_b_C3, "CPSRAI3_B_C3", MEPCOP1_32_INSN_CPSRAI3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpsrai3_h_C3, "CPSRAI3_H_C3", MEPCOP1_32_INSN_CPSRAI3_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpsrai3_w_C3, "CPSRAI3_W_C3", MEPCOP1_32_INSN_CPSRAI3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cdsrai3_C3, "CDSRAI3_C3", MEPCOP1_32_INSN_CDSRAI3_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpslli3_b_C3, "CPSLLI3_B_C3", MEPCOP1_32_INSN_CPSLLI3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpslli3_h_C3, "CPSLLI3_H_C3", MEPCOP1_32_INSN_CPSLLI3_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpslli3_w_C3, "CPSLLI3_W_C3", MEPCOP1_32_INSN_CPSLLI3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cdslli3_C3, "CDSLLI3_C3", MEPCOP1_32_INSN_CDSLLI3_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpslai3_h_C3, "CPSLAI3_H_C3", MEPCOP1_32_INSN_CPSLAI3_H_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpslai3_w_C3, "CPSLAI3_W_C3", MEPCOP1_32_INSN_CPSLAI3_W_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpclipiu3_w_C3, "CPCLIPIU3_W_C3", MEPCOP1_32_INSN_CPCLIPIU3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpclipi3_w_C3, "CPCLIPI3_W_C3", MEPCOP1_32_INSN_CPCLIPI3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cdclipiu3_C3, "CDCLIPIU3_C3", MEPCOP1_32_INSN_CDCLIPIU3_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cdclipi3_C3, "CDCLIPI3_C3", MEPCOP1_32_INSN_CDCLIPI3_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpmovi_b_C3, "CPMOVI_B_C3", MEPCOP1_32_INSN_CPMOVI_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpmoviu_h_C3, "CPMOVIU_H_C3", MEPCOP1_32_INSN_CPMOVIU_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4UHI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpmovi_h_C3, "CPMOVI_H_C3", MEPCOP1_32_INSN_CPMOVI_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpmoviu_w_C3, "CPMOVIU_W_C3", MEPCOP1_32_INSN_CPMOVIU_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2USI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpmovi_w_C3, "CPMOVI_W_C3", MEPCOP1_32_INSN_CPMOVI_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cdmoviu_C3, "CDMOVIU_C3", MEPCOP1_32_INSN_CDMOVIU_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cdmovi_C3, "CDMOVI_C3", MEPCOP1_32_INSN_CDMOVI_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpadda1u_b_C3, "CPADDA1U_B_C3", MEPCOP1_32_INSN_CPADDA1U_B_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8UQI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpadda1_b_C3, "CPADDA1_B_C3", MEPCOP1_32_INSN_CPADDA1_B_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpaddua1_h_C3, "CPADDUA1_H_C3", MEPCOP1_32_INSN_CPADDUA1_H_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpaddla1_h_C3, "CPADDLA1_H_C3", MEPCOP1_32_INSN_CPADDLA1_H_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpaddaca1u_b_C3, "CPADDACA1U_B_C3", MEPCOP1_32_INSN_CPADDACA1U_B_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8UQI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpaddaca1_b_C3, "CPADDACA1_B_C3", MEPCOP1_32_INSN_CPADDACA1_B_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpaddacua1_h_C3, "CPADDACUA1_H_C3", MEPCOP1_32_INSN_CPADDACUA1_H_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpaddacla1_h_C3, "CPADDACLA1_H_C3", MEPCOP1_32_INSN_CPADDACLA1_H_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpsuba1u_b_C3, "CPSUBA1U_B_C3", MEPCOP1_32_INSN_CPSUBA1U_B_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8UQI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpsuba1_b_C3, "CPSUBA1_B_C3", MEPCOP1_32_INSN_CPSUBA1_B_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpsubua1_h_C3, "CPSUBUA1_H_C3", MEPCOP1_32_INSN_CPSUBUA1_H_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpsubla1_h_C3, "CPSUBLA1_H_C3", MEPCOP1_32_INSN_CPSUBLA1_H_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpsubaca1u_b_C3, "CPSUBACA1U_B_C3", MEPCOP1_32_INSN_CPSUBACA1U_B_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8UQI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpsubaca1_b_C3, "CPSUBACA1_B_C3", MEPCOP1_32_INSN_CPSUBACA1_B_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpsubacua1_h_C3, "CPSUBACUA1_H_C3", MEPCOP1_32_INSN_CPSUBACUA1_H_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpsubacla1_h_C3, "CPSUBACLA1_H_C3", MEPCOP1_32_INSN_CPSUBACLA1_H_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpabsa1u_b_C3, "CPABSA1U_B_C3", MEPCOP1_32_INSN_CPABSA1U_B_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8UQI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpabsa1_b_C3, "CPABSA1_B_C3", MEPCOP1_32_INSN_CPABSA1_B_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpabsua1_h_C3, "CPABSUA1_H_C3", MEPCOP1_32_INSN_CPABSUA1_H_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpabsla1_h_C3, "CPABSLA1_H_C3", MEPCOP1_32_INSN_CPABSLA1_H_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpsada1u_b_C3, "CPSADA1U_B_C3", MEPCOP1_32_INSN_CPSADA1U_B_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8UQI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpsada1_b_C3, "CPSADA1_B_C3", MEPCOP1_32_INSN_CPSADA1_B_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpsadua1_h_C3, "CPSADUA1_H_C3", MEPCOP1_32_INSN_CPSADUA1_H_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpsadla1_h_C3, "CPSADLA1_H_C3", MEPCOP1_32_INSN_CPSADLA1_H_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpseta1_h_C3, "CPSETA1_H_C3", MEPCOP1_32_INSN_CPSETA1_H_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpsetua1_w_C3, "CPSETUA1_W_C3", MEPCOP1_32_INSN_CPSETUA1_W_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpsetla1_w_C3, "CPSETLA1_W_C3", MEPCOP1_32_INSN_CPSETLA1_W_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpmova1_b_C3, "CPMOVA1_B_C3", MEPCOP1_32_INSN_CPMOVA1_B_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpmovua1_h_C3, "CPMOVUA1_H_C3", MEPCOP1_32_INSN_CPMOVUA1_H_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpmovla1_h_C3, "CPMOVLA1_H_C3", MEPCOP1_32_INSN_CPMOVLA1_H_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpmovuua1_w_C3, "CPMOVUUA1_W_C3", MEPCOP1_32_INSN_CPMOVUUA1_W_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpmovula1_w_C3, "CPMOVULA1_W_C3", MEPCOP1_32_INSN_CPMOVULA1_W_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpmovlua1_w_C3, "CPMOVLUA1_W_C3", MEPCOP1_32_INSN_CPMOVLUA1_W_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpmovlla1_w_C3, "CPMOVLLA1_W_C3", MEPCOP1_32_INSN_CPMOVLLA1_W_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cppacka1u_b_C3, "CPPACKA1U_B_C3", MEPCOP1_32_INSN_CPPACKA1U_B_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8UQI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cppacka1_b_C3, "CPPACKA1_B_C3", MEPCOP1_32_INSN_CPPACKA1_B_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cppackua1_h_C3, "CPPACKUA1_H_C3", MEPCOP1_32_INSN_CPPACKUA1_H_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cppackla1_h_C3, "CPPACKLA1_H_C3", MEPCOP1_32_INSN_CPPACKLA1_H_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cppackua1_w_C3, "CPPACKUA1_W_C3", MEPCOP1_32_INSN_CPPACKUA1_W_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cppackla1_w_C3, "CPPACKLA1_W_C3", MEPCOP1_32_INSN_CPPACKLA1_W_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpmovhua1_w_C3, "CPMOVHUA1_W_C3", MEPCOP1_32_INSN_CPMOVHUA1_W_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpmovhla1_w_C3, "CPMOVHLA1_W_C3", MEPCOP1_32_INSN_CPMOVHLA1_W_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpsrla1_C3, "CPSRLA1_C3", MEPCOP1_32_INSN_CPSRLA1_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpsraa1_C3, "CPSRAA1_C3", MEPCOP1_32_INSN_CPSRAA1_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpslla1_C3, "CPSLLA1_C3", MEPCOP1_32_INSN_CPSLLA1_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpsrlia1_P1, "CPSRLIA1_P1", MEPCOP1_32_INSN_CPSRLIA1_P1, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpsraia1_P1, "CPSRAIA1_P1", MEPCOP1_32_INSN_CPSRAIA1_P1, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpsllia1_P1, "CPSLLIA1_P1", MEPCOP1_32_INSN_CPSLLIA1_P1, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpssqa1u_b_C3, "CPSSQA1U_B_C3", MEPCOP1_32_INSN_CPSSQA1U_B_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8UQI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpssqa1_b_C3, "CPSSQA1_B_C3", MEPCOP1_32_INSN_CPSSQA1_B_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpssda1u_b_C3, "CPSSDA1U_B_C3", MEPCOP1_32_INSN_CPSSDA1U_B_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8UQI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpssda1_b_C3, "CPSSDA1_B_C3", MEPCOP1_32_INSN_CPSSDA1_B_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpmula1u_b_C3, "CPMULA1U_B_C3", MEPCOP1_32_INSN_CPMULA1U_B_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8UQI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpmula1_b_C3, "CPMULA1_B_C3", MEPCOP1_32_INSN_CPMULA1_B_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpmulua1_h_C3, "CPMULUA1_H_C3", MEPCOP1_32_INSN_CPMULUA1_H_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpmulla1_h_C3, "CPMULLA1_H_C3", MEPCOP1_32_INSN_CPMULLA1_H_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpmulua1u_w_C3, "CPMULUA1U_W_C3", MEPCOP1_32_INSN_CPMULUA1U_W_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2USI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpmulla1u_w_C3, "CPMULLA1U_W_C3", MEPCOP1_32_INSN_CPMULLA1U_W_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2USI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpmulua1_w_C3, "CPMULUA1_W_C3", MEPCOP1_32_INSN_CPMULUA1_W_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpmulla1_w_C3, "CPMULLA1_W_C3", MEPCOP1_32_INSN_CPMULLA1_W_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpmada1u_b_C3, "CPMADA1U_B_C3", MEPCOP1_32_INSN_CPMADA1U_B_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8UQI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpmada1_b_C3, "CPMADA1_B_C3", MEPCOP1_32_INSN_CPMADA1_B_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpmadua1_h_C3, "CPMADUA1_H_C3", MEPCOP1_32_INSN_CPMADUA1_H_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpmadla1_h_C3, "CPMADLA1_H_C3", MEPCOP1_32_INSN_CPMADLA1_H_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpmadua1u_w_C3, "CPMADUA1U_W_C3", MEPCOP1_32_INSN_CPMADUA1U_W_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2USI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpmadla1u_w_C3, "CPMADLA1U_W_C3", MEPCOP1_32_INSN_CPMADLA1U_W_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2USI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpmadua1_w_C3, "CPMADUA1_W_C3", MEPCOP1_32_INSN_CPMADUA1_W_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpmadla1_w_C3, "CPMADLA1_W_C3", MEPCOP1_32_INSN_CPMADLA1_W_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpmsbua1_h_C3, "CPMSBUA1_H_C3", MEPCOP1_32_INSN_CPMSBUA1_H_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpmsbla1_h_C3, "CPMSBLA1_H_C3", MEPCOP1_32_INSN_CPMSBLA1_H_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpmsbua1u_w_C3, "CPMSBUA1U_W_C3", MEPCOP1_32_INSN_CPMSBUA1U_W_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2USI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpmsbla1u_w_C3, "CPMSBLA1U_W_C3", MEPCOP1_32_INSN_CPMSBLA1U_W_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2USI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpmsbua1_w_C3, "CPMSBUA1_W_C3", MEPCOP1_32_INSN_CPMSBUA1_W_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpmsbla1_w_C3, "CPMSBLA1_W_C3", MEPCOP1_32_INSN_CPMSBLA1_W_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpsmadua1_h_C3, "CPSMADUA1_H_C3", MEPCOP1_32_INSN_CPSMADUA1_H_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpsmadla1_h_C3, "CPSMADLA1_H_C3", MEPCOP1_32_INSN_CPSMADLA1_H_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpsmadua1_w_C3, "CPSMADUA1_W_C3", MEPCOP1_32_INSN_CPSMADUA1_W_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpsmadla1_w_C3, "CPSMADLA1_W_C3", MEPCOP1_32_INSN_CPSMADLA1_W_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpsmsbua1_h_C3, "CPSMSBUA1_H_C3", MEPCOP1_32_INSN_CPSMSBUA1_H_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpsmsbla1_h_C3, "CPSMSBLA1_H_C3", MEPCOP1_32_INSN_CPSMSBLA1_H_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpsmsbua1_w_C3, "CPSMSBUA1_W_C3", MEPCOP1_32_INSN_CPSMSBUA1_W_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpsmsbla1_w_C3, "CPSMSBLA1_W_C3", MEPCOP1_32_INSN_CPSMSBLA1_W_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpmulslua1_h_C3, "CPMULSLUA1_H_C3", MEPCOP1_32_INSN_CPMULSLUA1_H_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpmulslla1_h_C3, "CPMULSLLA1_H_C3", MEPCOP1_32_INSN_CPMULSLLA1_H_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpmulslua1_w_C3, "CPMULSLUA1_W_C3", MEPCOP1_32_INSN_CPMULSLUA1_W_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpmulslla1_w_C3, "CPMULSLLA1_W_C3", MEPCOP1_32_INSN_CPMULSLLA1_W_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpsmadslua1_h_C3, "CPSMADSLUA1_H_C3", MEPCOP1_32_INSN_CPSMADSLUA1_H_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpsmadslla1_h_C3, "CPSMADSLLA1_H_C3", MEPCOP1_32_INSN_CPSMADSLLA1_H_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpsmadslua1_w_C3, "CPSMADSLUA1_W_C3", MEPCOP1_32_INSN_CPSMADSLUA1_W_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpsmadslla1_w_C3, "CPSMADSLLA1_W_C3", MEPCOP1_32_INSN_CPSMADSLLA1_W_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpsmsbslua1_h_C3, "CPSMSBSLUA1_H_C3", MEPCOP1_32_INSN_CPSMSBSLUA1_H_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpsmsbslla1_h_C3, "CPSMSBSLLA1_H_C3", MEPCOP1_32_INSN_CPSMSBSLLA1_H_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpsmsbslua1_w_C3, "CPSMSBSLUA1_W_C3", MEPCOP1_32_INSN_CPSMSBSLUA1_W_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+  { mepcop1_32_sem_cpsmsbslla1_w_C3, "CPSMSBSLLA1_W_C3", MEPCOP1_32_INSN_CPSMSBSLLA1_W_C3, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
 
 };
 
@@ -350,10 +350,16 @@ mepcop1_32_extract_sfmt_cpadd3_b_C3 (mepcop1_32_scache* abuf, mep_ext1_cpu* curr
 static void
 mepcop1_32_extract_sfmt_cpfsftbi_C3 (mepcop1_32_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_32_insn_word base_insn, mepcop1_32_insn_word entire_insn);
 static void
+mepcop1_32_extract_sfmt_cpssub3_h_C3 (mepcop1_32_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_32_insn_word base_insn, mepcop1_32_insn_word entire_insn);
+static void
 mepcop1_32_extract_sfmt_cpmovfrcsar0_C3 (mepcop1_32_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_32_insn_word base_insn, mepcop1_32_insn_word entire_insn);
 static void
 mepcop1_32_extract_sfmt_cpmovtocsar0_C3 (mepcop1_32_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_32_insn_word base_insn, mepcop1_32_insn_word entire_insn);
 static void
+mepcop1_32_extract_sfmt_cpmovtocsar1_C3 (mepcop1_32_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_32_insn_word base_insn, mepcop1_32_insn_word entire_insn);
+static void
+mepcop1_32_extract_sfmt_cpmovtocc_C3 (mepcop1_32_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_32_insn_word base_insn, mepcop1_32_insn_word entire_insn);
+static void
 mepcop1_32_extract_sfmt_cpmov_C3 (mepcop1_32_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_32_insn_word base_insn, mepcop1_32_insn_word entire_insn);
 static void
 mepcop1_32_extract_sfmt_cpccadd_b_C3 (mepcop1_32_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_32_insn_word base_insn, mepcop1_32_insn_word entire_insn);
@@ -372,6 +378,20 @@ mepcop1_32_extract_sfmt_cpmovi_b_C3 (mepcop1_32_scache* abuf, mep_ext1_cpu* curr
 static void
 mepcop1_32_extract_sfmt_cpmoviu_h_C3 (mepcop1_32_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_32_insn_word base_insn, mepcop1_32_insn_word entire_insn);
 static void
+mepcop1_32_extract_sfmt_cpadda1u_b_C3 (mepcop1_32_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_32_insn_word base_insn, mepcop1_32_insn_word entire_insn);
+static void
+mepcop1_32_extract_sfmt_cpaddua1_h_C3 (mepcop1_32_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_32_insn_word base_insn, mepcop1_32_insn_word entire_insn);
+static void
+mepcop1_32_extract_sfmt_cpaddla1_h_C3 (mepcop1_32_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_32_insn_word base_insn, mepcop1_32_insn_word entire_insn);
+static void
+mepcop1_32_extract_sfmt_cpaddaca1u_b_C3 (mepcop1_32_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_32_insn_word base_insn, mepcop1_32_insn_word entire_insn);
+static void
+mepcop1_32_extract_sfmt_cpaddacua1_h_C3 (mepcop1_32_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_32_insn_word base_insn, mepcop1_32_insn_word entire_insn);
+static void
+mepcop1_32_extract_sfmt_cpaddacla1_h_C3 (mepcop1_32_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_32_insn_word base_insn, mepcop1_32_insn_word entire_insn);
+static void
+mepcop1_32_extract_sfmt_cpsrla1_C3 (mepcop1_32_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_32_insn_word base_insn, mepcop1_32_insn_word entire_insn);
+static void
 mepcop1_32_extract_sfmt_cpsrlia1_P1 (mepcop1_32_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_32_insn_word base_insn, mepcop1_32_insn_word entire_insn);
 
 // Fetch & decode instruction
@@ -402,35 +422,35 @@ mepcop1_32_scache::decode (mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_32_insn
           {
           case 0 :
             if ((entire_insn & 0xfffff801) == 0xf0070001)
-              { itype = MEPCOP1_32_INSN_CPADDA1U_B_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+              { itype = MEPCOP1_32_INSN_CPADDA1U_B_C3; mepcop1_32_extract_sfmt_cpadda1u_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
             itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           case 1 :
             if ((entire_insn & 0xfffff801) == 0xf0170001)
-              { itype = MEPCOP1_32_INSN_CPADDA1_B_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+              { itype = MEPCOP1_32_INSN_CPADDA1_B_C3; mepcop1_32_extract_sfmt_cpadda1u_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
             itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           case 2 :
             if ((entire_insn & 0xfffff801) == 0xf0470001)
-              { itype = MEPCOP1_32_INSN_CPADDACA1U_B_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+              { itype = MEPCOP1_32_INSN_CPADDACA1U_B_C3; mepcop1_32_extract_sfmt_cpaddaca1u_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
             itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           case 3 :
             if ((entire_insn & 0xfffff801) == 0xf0570001)
-              { itype = MEPCOP1_32_INSN_CPADDACA1_B_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+              { itype = MEPCOP1_32_INSN_CPADDACA1_B_C3; mepcop1_32_extract_sfmt_cpaddaca1u_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
             itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           case 4 :
             if ((entire_insn & 0xfffff801) == 0xf0870001)
-              { itype = MEPCOP1_32_INSN_CPSUBA1U_B_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+              { itype = MEPCOP1_32_INSN_CPSUBA1U_B_C3; mepcop1_32_extract_sfmt_cpadda1u_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
             itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           case 5 :
             if ((entire_insn & 0xfffff801) == 0xf0970001)
-              { itype = MEPCOP1_32_INSN_CPSUBA1_B_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+              { itype = MEPCOP1_32_INSN_CPSUBA1_B_C3; mepcop1_32_extract_sfmt_cpadda1u_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
             itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           case 6 :
             if ((entire_insn & 0xfffff801) == 0xf0c70001)
-              { itype = MEPCOP1_32_INSN_CPSUBACA1U_B_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+              { itype = MEPCOP1_32_INSN_CPSUBACA1U_B_C3; mepcop1_32_extract_sfmt_cpaddaca1u_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
             itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           case 7 :
             if ((entire_insn & 0xfffff801) == 0xf0d70001)
-              { itype = MEPCOP1_32_INSN_CPSUBACA1_B_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+              { itype = MEPCOP1_32_INSN_CPSUBACA1_B_C3; mepcop1_32_extract_sfmt_cpaddaca1u_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
             itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           default : itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           }
@@ -449,35 +469,35 @@ mepcop1_32_scache::decode (mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_32_insn
           {
           case 0 :
             if ((entire_insn & 0xfffff801) == 0xf0070801)
-              { itype = MEPCOP1_32_INSN_CPSSQA1U_B_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+              { itype = MEPCOP1_32_INSN_CPSSQA1U_B_C3; mepcop1_32_extract_sfmt_cpadda1u_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
             itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           case 1 :
             if ((entire_insn & 0xfffff801) == 0xf0170801)
-              { itype = MEPCOP1_32_INSN_CPSSQA1_B_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+              { itype = MEPCOP1_32_INSN_CPSSQA1_B_C3; mepcop1_32_extract_sfmt_cpadda1u_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
             itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           case 2 :
             if ((entire_insn & 0xfffff801) == 0xf0470801)
-              { itype = MEPCOP1_32_INSN_CPSSDA1U_B_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+              { itype = MEPCOP1_32_INSN_CPSSDA1U_B_C3; mepcop1_32_extract_sfmt_cpaddaca1u_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
             itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           case 3 :
             if ((entire_insn & 0xfffff801) == 0xf0570801)
-              { itype = MEPCOP1_32_INSN_CPSSDA1_B_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+              { itype = MEPCOP1_32_INSN_CPSSDA1_B_C3; mepcop1_32_extract_sfmt_cpaddaca1u_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
             itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           case 4 :
             if ((entire_insn & 0xfffff801) == 0xf0870801)
-              { itype = MEPCOP1_32_INSN_CPMULA1U_B_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+              { itype = MEPCOP1_32_INSN_CPMULA1U_B_C3; mepcop1_32_extract_sfmt_cpadda1u_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
             itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           case 5 :
             if ((entire_insn & 0xfffff801) == 0xf0970801)
-              { itype = MEPCOP1_32_INSN_CPMULA1_B_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+              { itype = MEPCOP1_32_INSN_CPMULA1_B_C3; mepcop1_32_extract_sfmt_cpadda1u_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
             itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           case 6 :
             if ((entire_insn & 0xfffff801) == 0xf0c70801)
-              { itype = MEPCOP1_32_INSN_CPMULUA1U_W_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+              { itype = MEPCOP1_32_INSN_CPMULUA1U_W_C3; mepcop1_32_extract_sfmt_cpaddua1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
             itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           case 7 :
             if ((entire_insn & 0xfffff801) == 0xf0d70801)
-              { itype = MEPCOP1_32_INSN_CPMULLA1U_W_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+              { itype = MEPCOP1_32_INSN_CPMULLA1U_W_C3; mepcop1_32_extract_sfmt_cpaddla1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
             itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           default : itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           }
@@ -496,11 +516,11 @@ mepcop1_32_scache::decode (mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_32_insn
           {
           case 0 :
             if ((entire_insn & 0xfffff83f) == 0xf0071001)
-              { itype = MEPCOP1_32_INSN_CPSRLA1_C3; mepcop1_32_extract_sfmt_cpmovtocsar0_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+              { itype = MEPCOP1_32_INSN_CPSRLA1_C3; mepcop1_32_extract_sfmt_cpsrla1_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
             itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           case 1 :
             if ((entire_insn & 0xfffff83f) == 0xf0171001)
-              { itype = MEPCOP1_32_INSN_CPSRAA1_C3; mepcop1_32_extract_sfmt_cpmovtocsar0_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+              { itype = MEPCOP1_32_INSN_CPSRAA1_C3; mepcop1_32_extract_sfmt_cpsrla1_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
             itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           default : itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           }
@@ -666,11 +686,11 @@ mepcop1_32_scache::decode (mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_32_insn
             itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           case 17 :
             if ((entire_insn & 0xfffff83f) == 0xf0078022)
-              { itype = MEPCOP1_32_INSN_CPMOVTOCC_C3; mepcop1_32_extract_sfmt_cpmovtocsar0_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+              { itype = MEPCOP1_32_INSN_CPMOVTOCC_C3; mepcop1_32_extract_sfmt_cpmovtocc_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
             itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           case 31 :
             if ((entire_insn & 0xfffff83f) == 0xf007803e)
-              { itype = MEPCOP1_32_INSN_CPMOVTOCSAR1_C3; mepcop1_32_extract_sfmt_cpmovtocsar0_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+              { itype = MEPCOP1_32_INSN_CPMOVTOCSAR1_C3; mepcop1_32_extract_sfmt_cpmovtocsar1_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
             itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           default : itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           }
@@ -1097,35 +1117,35 @@ mepcop1_32_scache::decode (mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_32_insn
           {
           case 0 :
             if ((entire_insn & 0xfffff801) == 0xf0270001)
-              { itype = MEPCOP1_32_INSN_CPADDUA1_H_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+              { itype = MEPCOP1_32_INSN_CPADDUA1_H_C3; mepcop1_32_extract_sfmt_cpaddua1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
             itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           case 1 :
             if ((entire_insn & 0xfffff801) == 0xf0370001)
-              { itype = MEPCOP1_32_INSN_CPADDLA1_H_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+              { itype = MEPCOP1_32_INSN_CPADDLA1_H_C3; mepcop1_32_extract_sfmt_cpaddla1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
             itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           case 2 :
             if ((entire_insn & 0xfffff801) == 0xf0670001)
-              { itype = MEPCOP1_32_INSN_CPADDACUA1_H_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+              { itype = MEPCOP1_32_INSN_CPADDACUA1_H_C3; mepcop1_32_extract_sfmt_cpaddacua1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
             itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           case 3 :
             if ((entire_insn & 0xfffff801) == 0xf0770001)
-              { itype = MEPCOP1_32_INSN_CPADDACLA1_H_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+              { itype = MEPCOP1_32_INSN_CPADDACLA1_H_C3; mepcop1_32_extract_sfmt_cpaddacla1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
             itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           case 4 :
             if ((entire_insn & 0xfffff801) == 0xf0a70001)
-              { itype = MEPCOP1_32_INSN_CPSUBUA1_H_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+              { itype = MEPCOP1_32_INSN_CPSUBUA1_H_C3; mepcop1_32_extract_sfmt_cpaddua1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
             itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           case 5 :
             if ((entire_insn & 0xfffff801) == 0xf0b70001)
-              { itype = MEPCOP1_32_INSN_CPSUBLA1_H_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+              { itype = MEPCOP1_32_INSN_CPSUBLA1_H_C3; mepcop1_32_extract_sfmt_cpaddla1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
             itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           case 6 :
             if ((entire_insn & 0xfffff801) == 0xf0e70001)
-              { itype = MEPCOP1_32_INSN_CPSUBACUA1_H_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+              { itype = MEPCOP1_32_INSN_CPSUBACUA1_H_C3; mepcop1_32_extract_sfmt_cpaddacua1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
             itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           case 7 :
             if ((entire_insn & 0xfffff801) == 0xf0f70001)
-              { itype = MEPCOP1_32_INSN_CPSUBACLA1_H_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+              { itype = MEPCOP1_32_INSN_CPSUBACLA1_H_C3; mepcop1_32_extract_sfmt_cpaddacla1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
             itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           default : itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           }
@@ -1137,26 +1157,26 @@ mepcop1_32_scache::decode (mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_32_insn
           {
           case 0 :
             if ((entire_insn & 0xfffff801) == 0xf0a70801)
-              { itype = MEPCOP1_32_INSN_CPMULUA1_H_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+              { itype = MEPCOP1_32_INSN_CPMULUA1_H_C3; mepcop1_32_extract_sfmt_cpaddua1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
             itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           case 1 :
             if ((entire_insn & 0xfffff801) == 0xf0b70801)
-              { itype = MEPCOP1_32_INSN_CPMULLA1_H_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+              { itype = MEPCOP1_32_INSN_CPMULLA1_H_C3; mepcop1_32_extract_sfmt_cpaddla1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
             itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           case 2 :
             if ((entire_insn & 0xfffff801) == 0xf0e70801)
-              { itype = MEPCOP1_32_INSN_CPMULUA1_W_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+              { itype = MEPCOP1_32_INSN_CPMULUA1_W_C3; mepcop1_32_extract_sfmt_cpaddua1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
             itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           case 3 :
             if ((entire_insn & 0xfffff801) == 0xf0f70801)
-              { itype = MEPCOP1_32_INSN_CPMULLA1_W_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+              { itype = MEPCOP1_32_INSN_CPMULLA1_W_C3; mepcop1_32_extract_sfmt_cpaddla1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
             itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           default : itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           }
         }
       case 69 :
         if ((entire_insn & 0xfffff83f) == 0xf0271001)
-          { itype = MEPCOP1_32_INSN_CPSLLA1_C3; mepcop1_32_extract_sfmt_cpmovtocsar0_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+          { itype = MEPCOP1_32_INSN_CPSLLA1_C3; mepcop1_32_extract_sfmt_cpsrla1_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
         itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
       case 96 : /* fall through */
       case 160 : /* fall through */
@@ -1203,19 +1223,19 @@ mepcop1_32_scache::decode (mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_32_insn
           {
           case 0 :
             if ((entire_insn & 0xfffff801) == 0xf1070001)
-              { itype = MEPCOP1_32_INSN_CPABSA1U_B_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+              { itype = MEPCOP1_32_INSN_CPABSA1U_B_C3; mepcop1_32_extract_sfmt_cpadda1u_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
             itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           case 1 :
             if ((entire_insn & 0xfffff801) == 0xf1170001)
-              { itype = MEPCOP1_32_INSN_CPABSA1_B_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+              { itype = MEPCOP1_32_INSN_CPABSA1_B_C3; mepcop1_32_extract_sfmt_cpadda1u_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
             itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           case 2 :
             if ((entire_insn & 0xfffff801) == 0xf1470001)
-              { itype = MEPCOP1_32_INSN_CPSADA1U_B_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+              { itype = MEPCOP1_32_INSN_CPSADA1U_B_C3; mepcop1_32_extract_sfmt_cpaddaca1u_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
             itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           case 3 :
             if ((entire_insn & 0xfffff801) == 0xf1570001)
-              { itype = MEPCOP1_32_INSN_CPSADA1_B_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+              { itype = MEPCOP1_32_INSN_CPSADA1_B_C3; mepcop1_32_extract_sfmt_cpaddaca1u_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
             itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           default : itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           }
@@ -1227,27 +1247,27 @@ mepcop1_32_scache::decode (mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_32_insn
           {
           case 0 :
             if ((entire_insn & 0xfffff801) == 0xf1070801)
-              { itype = MEPCOP1_32_INSN_CPMADA1U_B_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+              { itype = MEPCOP1_32_INSN_CPMADA1U_B_C3; mepcop1_32_extract_sfmt_cpaddaca1u_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
             itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           case 1 :
             if ((entire_insn & 0xfffff801) == 0xf1170801)
-              { itype = MEPCOP1_32_INSN_CPMADA1_B_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+              { itype = MEPCOP1_32_INSN_CPMADA1_B_C3; mepcop1_32_extract_sfmt_cpaddaca1u_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
             itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           case 2 :
             if ((entire_insn & 0xfffff801) == 0xf1470801)
-              { itype = MEPCOP1_32_INSN_CPMADUA1U_W_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+              { itype = MEPCOP1_32_INSN_CPMADUA1U_W_C3; mepcop1_32_extract_sfmt_cpaddacua1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
             itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           case 3 :
             if ((entire_insn & 0xfffff801) == 0xf1570801)
-              { itype = MEPCOP1_32_INSN_CPMADLA1U_W_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+              { itype = MEPCOP1_32_INSN_CPMADLA1U_W_C3; mepcop1_32_extract_sfmt_cpaddacla1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
             itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           case 6 :
             if ((entire_insn & 0xfffff801) == 0xf1c70801)
-              { itype = MEPCOP1_32_INSN_CPMSBUA1U_W_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+              { itype = MEPCOP1_32_INSN_CPMSBUA1U_W_C3; mepcop1_32_extract_sfmt_cpaddacua1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
             itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           case 7 :
             if ((entire_insn & 0xfffff801) == 0xf1d70801)
-              { itype = MEPCOP1_32_INSN_CPMSBLA1U_W_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+              { itype = MEPCOP1_32_INSN_CPMSBLA1U_W_C3; mepcop1_32_extract_sfmt_cpaddacla1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
             itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           default : itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           }
@@ -1299,19 +1319,19 @@ mepcop1_32_scache::decode (mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_32_insn
           {
           case 0 :
             if ((entire_insn & 0xfffff801) == 0xf1270001)
-              { itype = MEPCOP1_32_INSN_CPABSUA1_H_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+              { itype = MEPCOP1_32_INSN_CPABSUA1_H_C3; mepcop1_32_extract_sfmt_cpaddua1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
             itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           case 1 :
             if ((entire_insn & 0xfffff801) == 0xf1370001)
-              { itype = MEPCOP1_32_INSN_CPABSLA1_H_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+              { itype = MEPCOP1_32_INSN_CPABSLA1_H_C3; mepcop1_32_extract_sfmt_cpaddla1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
             itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           case 2 :
             if ((entire_insn & 0xfffff801) == 0xf1670001)
-              { itype = MEPCOP1_32_INSN_CPSADUA1_H_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+              { itype = MEPCOP1_32_INSN_CPSADUA1_H_C3; mepcop1_32_extract_sfmt_cpaddacua1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
             itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           case 3 :
             if ((entire_insn & 0xfffff801) == 0xf1770001)
-              { itype = MEPCOP1_32_INSN_CPSADLA1_H_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+              { itype = MEPCOP1_32_INSN_CPSADLA1_H_C3; mepcop1_32_extract_sfmt_cpaddacla1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
             itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           default : itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           }
@@ -1323,35 +1343,35 @@ mepcop1_32_scache::decode (mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_32_insn
           {
           case 0 :
             if ((entire_insn & 0xfffff801) == 0xf1270801)
-              { itype = MEPCOP1_32_INSN_CPMADUA1_H_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+              { itype = MEPCOP1_32_INSN_CPMADUA1_H_C3; mepcop1_32_extract_sfmt_cpaddacua1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
             itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           case 1 :
             if ((entire_insn & 0xfffff801) == 0xf1370801)
-              { itype = MEPCOP1_32_INSN_CPMADLA1_H_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+              { itype = MEPCOP1_32_INSN_CPMADLA1_H_C3; mepcop1_32_extract_sfmt_cpaddacla1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
             itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           case 2 :
             if ((entire_insn & 0xfffff801) == 0xf1670801)
-              { itype = MEPCOP1_32_INSN_CPMADUA1_W_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+              { itype = MEPCOP1_32_INSN_CPMADUA1_W_C3; mepcop1_32_extract_sfmt_cpaddacua1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
             itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           case 3 :
             if ((entire_insn & 0xfffff801) == 0xf1770801)
-              { itype = MEPCOP1_32_INSN_CPMADLA1_W_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+              { itype = MEPCOP1_32_INSN_CPMADLA1_W_C3; mepcop1_32_extract_sfmt_cpaddacla1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
             itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           case 4 :
             if ((entire_insn & 0xfffff801) == 0xf1a70801)
-              { itype = MEPCOP1_32_INSN_CPMSBUA1_H_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+              { itype = MEPCOP1_32_INSN_CPMSBUA1_H_C3; mepcop1_32_extract_sfmt_cpaddacua1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
             itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           case 5 :
             if ((entire_insn & 0xfffff801) == 0xf1b70801)
-              { itype = MEPCOP1_32_INSN_CPMSBLA1_H_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+              { itype = MEPCOP1_32_INSN_CPMSBLA1_H_C3; mepcop1_32_extract_sfmt_cpaddacla1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
             itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           case 6 :
             if ((entire_insn & 0xfffff801) == 0xf1e70801)
-              { itype = MEPCOP1_32_INSN_CPMSBUA1_W_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+              { itype = MEPCOP1_32_INSN_CPMSBUA1_W_C3; mepcop1_32_extract_sfmt_cpaddacua1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
             itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           case 7 :
             if ((entire_insn & 0xfffff801) == 0xf1f70801)
-              { itype = MEPCOP1_32_INSN_CPMSBLA1_W_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+              { itype = MEPCOP1_32_INSN_CPMSBLA1_W_C3; mepcop1_32_extract_sfmt_cpaddacla1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
             itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           default : itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           }
@@ -1381,7 +1401,7 @@ mepcop1_32_scache::decode (mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_32_insn
         itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
       case 257 :
         if ((entire_insn & 0xfffff801) == 0xf2070001)
-          { itype = MEPCOP1_32_INSN_CPSETA1_H_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+          { itype = MEPCOP1_32_INSN_CPSETA1_H_C3; mepcop1_32_extract_sfmt_cpadda1u_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
         itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
       case 258 : /* fall through */
       case 322 : /* fall through */
@@ -1484,11 +1504,11 @@ mepcop1_32_scache::decode (mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_32_insn
           {
           case 0 :
             if ((entire_insn & 0xfffff801) == 0xf2270001)
-              { itype = MEPCOP1_32_INSN_CPSETUA1_W_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+              { itype = MEPCOP1_32_INSN_CPSETUA1_W_C3; mepcop1_32_extract_sfmt_cpaddua1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
             itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           case 1 :
             if ((entire_insn & 0xfffff801) == 0xf2370001)
-              { itype = MEPCOP1_32_INSN_CPSETLA1_W_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+              { itype = MEPCOP1_32_INSN_CPSETLA1_W_C3; mepcop1_32_extract_sfmt_cpaddla1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
             itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           default : itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           }
@@ -1556,35 +1576,35 @@ mepcop1_32_scache::decode (mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_32_insn
           {
           case 0 :
             if ((entire_insn & 0xfffff801) == 0xf3270801)
-              { itype = MEPCOP1_32_INSN_CPSMADUA1_H_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+              { itype = MEPCOP1_32_INSN_CPSMADUA1_H_C3; mepcop1_32_extract_sfmt_cpaddacua1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
             itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           case 1 :
             if ((entire_insn & 0xfffff801) == 0xf3370801)
-              { itype = MEPCOP1_32_INSN_CPSMADLA1_H_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+              { itype = MEPCOP1_32_INSN_CPSMADLA1_H_C3; mepcop1_32_extract_sfmt_cpaddacla1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
             itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           case 2 :
             if ((entire_insn & 0xfffff801) == 0xf3670801)
-              { itype = MEPCOP1_32_INSN_CPSMADUA1_W_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+              { itype = MEPCOP1_32_INSN_CPSMADUA1_W_C3; mepcop1_32_extract_sfmt_cpaddacua1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
             itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           case 3 :
             if ((entire_insn & 0xfffff801) == 0xf3770801)
-              { itype = MEPCOP1_32_INSN_CPSMADLA1_W_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+              { itype = MEPCOP1_32_INSN_CPSMADLA1_W_C3; mepcop1_32_extract_sfmt_cpaddacla1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
             itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           case 4 :
             if ((entire_insn & 0xfffff801) == 0xf3a70801)
-              { itype = MEPCOP1_32_INSN_CPSMSBUA1_H_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+              { itype = MEPCOP1_32_INSN_CPSMSBUA1_H_C3; mepcop1_32_extract_sfmt_cpaddacua1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
             itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           case 5 :
             if ((entire_insn & 0xfffff801) == 0xf3b70801)
-              { itype = MEPCOP1_32_INSN_CPSMSBLA1_H_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+              { itype = MEPCOP1_32_INSN_CPSMSBLA1_H_C3; mepcop1_32_extract_sfmt_cpaddacla1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
             itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           case 6 :
             if ((entire_insn & 0xfffff801) == 0xf3e70801)
-              { itype = MEPCOP1_32_INSN_CPSMSBUA1_W_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+              { itype = MEPCOP1_32_INSN_CPSMSBUA1_W_C3; mepcop1_32_extract_sfmt_cpaddacua1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
             itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           case 7 :
             if ((entire_insn & 0xfffff801) == 0xf3f70801)
-              { itype = MEPCOP1_32_INSN_CPSMSBLA1_W_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+              { itype = MEPCOP1_32_INSN_CPSMSBLA1_W_C3; mepcop1_32_extract_sfmt_cpaddacla1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
             itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           default : itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           }
@@ -1779,19 +1799,19 @@ mepcop1_32_scache::decode (mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_32_insn
           {
           case 0 :
             if ((entire_insn & 0xfffff801) == 0xf4a70801)
-              { itype = MEPCOP1_32_INSN_CPMULSLUA1_H_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+              { itype = MEPCOP1_32_INSN_CPMULSLUA1_H_C3; mepcop1_32_extract_sfmt_cpaddacua1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
             itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           case 1 :
             if ((entire_insn & 0xfffff801) == 0xf4b70801)
-              { itype = MEPCOP1_32_INSN_CPMULSLLA1_H_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+              { itype = MEPCOP1_32_INSN_CPMULSLLA1_H_C3; mepcop1_32_extract_sfmt_cpaddacla1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
             itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           case 2 :
             if ((entire_insn & 0xfffff801) == 0xf4e70801)
-              { itype = MEPCOP1_32_INSN_CPMULSLUA1_W_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+              { itype = MEPCOP1_32_INSN_CPMULSLUA1_W_C3; mepcop1_32_extract_sfmt_cpaddacua1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
             itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           case 3 :
             if ((entire_insn & 0xfffff801) == 0xf4f70801)
-              { itype = MEPCOP1_32_INSN_CPMULSLLA1_W_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+              { itype = MEPCOP1_32_INSN_CPMULSLLA1_W_C3; mepcop1_32_extract_sfmt_cpaddacla1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
             itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           default : itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           }
@@ -1945,35 +1965,35 @@ mepcop1_32_scache::decode (mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_32_insn
           {
           case 0 :
             if ((entire_insn & 0xfffff801) == 0xf7270801)
-              { itype = MEPCOP1_32_INSN_CPSMADSLUA1_H_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+              { itype = MEPCOP1_32_INSN_CPSMADSLUA1_H_C3; mepcop1_32_extract_sfmt_cpaddacua1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
             itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           case 1 :
             if ((entire_insn & 0xfffff801) == 0xf7370801)
-              { itype = MEPCOP1_32_INSN_CPSMADSLLA1_H_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+              { itype = MEPCOP1_32_INSN_CPSMADSLLA1_H_C3; mepcop1_32_extract_sfmt_cpaddacla1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
             itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           case 2 :
             if ((entire_insn & 0xfffff801) == 0xf7670801)
-              { itype = MEPCOP1_32_INSN_CPSMADSLUA1_W_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+              { itype = MEPCOP1_32_INSN_CPSMADSLUA1_W_C3; mepcop1_32_extract_sfmt_cpaddacua1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
             itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           case 3 :
             if ((entire_insn & 0xfffff801) == 0xf7770801)
-              { itype = MEPCOP1_32_INSN_CPSMADSLLA1_W_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+              { itype = MEPCOP1_32_INSN_CPSMADSLLA1_W_C3; mepcop1_32_extract_sfmt_cpaddacla1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
             itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           case 4 :
             if ((entire_insn & 0xfffff801) == 0xf7a70801)
-              { itype = MEPCOP1_32_INSN_CPSMSBSLUA1_H_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+              { itype = MEPCOP1_32_INSN_CPSMSBSLUA1_H_C3; mepcop1_32_extract_sfmt_cpaddacua1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
             itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           case 5 :
             if ((entire_insn & 0xfffff801) == 0xf7b70801)
-              { itype = MEPCOP1_32_INSN_CPSMSBSLLA1_H_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+              { itype = MEPCOP1_32_INSN_CPSMSBSLLA1_H_C3; mepcop1_32_extract_sfmt_cpaddacla1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
             itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           case 6 :
             if ((entire_insn & 0xfffff801) == 0xf7e70801)
-              { itype = MEPCOP1_32_INSN_CPSMSBSLUA1_W_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+              { itype = MEPCOP1_32_INSN_CPSMSBSLUA1_W_C3; mepcop1_32_extract_sfmt_cpaddacua1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
             itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           case 7 :
             if ((entire_insn & 0xfffff801) == 0xf7f70801)
-              { itype = MEPCOP1_32_INSN_CPSMSBSLLA1_W_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+              { itype = MEPCOP1_32_INSN_CPSMSBSLLA1_W_C3; mepcop1_32_extract_sfmt_cpaddacla1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
             itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           default : itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
           }
@@ -2245,7 +2265,7 @@ mepcop1_32_scache::decode (mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_32_insn
       case 1680 : /* fall through */
       case 1744 :
         if ((entire_insn & 0xfe0ff801) == 0xfc074000)
-          { itype = MEPCOP1_32_INSN_CPSSUB3_H_C3; mepcop1_32_extract_sfmt_cpadd3_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+          { itype = MEPCOP1_32_INSN_CPSSUB3_H_C3; mepcop1_32_extract_sfmt_cpssub3_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
         itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
       case 1554 : /* fall through */
       case 1618 : /* fall through */
@@ -2331,7 +2351,7 @@ mepcop1_32_scache::decode (mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_32_insn
       case 1936 : /* fall through */
       case 2000 :
         if ((entire_insn & 0xfe0ff801) == 0xfe074000)
-          { itype = MEPCOP1_32_INSN_CPSSUB3_W_C3; mepcop1_32_extract_sfmt_cpadd3_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+          { itype = MEPCOP1_32_INSN_CPSSUB3_W_C3; mepcop1_32_extract_sfmt_cpssub3_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
         itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
       case 1810 : /* fall through */
       case 1874 : /* fall through */
@@ -2591,6 +2611,39 @@ mepcop1_32_extract_sfmt_cpfsftbi_C3 (mepcop1_32_scache* abuf, mep_ext1_cpu* curr
 }
 
 void
+mepcop1_32_extract_sfmt_cpssub3_h_C3 (mepcop1_32_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_32_insn_word base_insn, mepcop1_32_insn_word entire_insn){
+    mepcop1_32_insn_word insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cpfsftbi_C3.f
+    UINT f_ivc2_5u7;
+    UINT f_ivc2_5u21;
+    UINT f_ivc2_5u26;
+
+    f_ivc2_5u7 = EXTRACT_MSB0_UINT (insn, 32, 7, 5);
+    f_ivc2_5u21 = EXTRACT_MSB0_UINT (insn, 32, 21, 5);
+    f_ivc2_5u26 = EXTRACT_MSB0_UINT (insn, 32, 26, 5);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_ivc2_5u26) = f_ivc2_5u26;
+  FLD (f_ivc2_5u21) = f_ivc2_5u21;
+  FLD (f_ivc2_5u7) = f_ivc2_5u7;
+  if (UNLIKELY(current_cpu->trace_extract_p))
+    {
+      current_cpu->trace_stream 
+        << "0x" << hex << pc << dec << " (sfmt_cpssub3_h_C3)\t"
+        << " f_ivc2_5u26:0x" << hex << f_ivc2_5u26 << dec
+        << " f_ivc2_5u21:0x" << hex << f_ivc2_5u21 << dec
+        << " f_ivc2_5u7:0x" << hex << f_ivc2_5u7 << dec
+        << endl;
+    }
+
+  /* Record the fields for profiling.  */
+  if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
+    {
+    }
+#undef FLD
+}
+
+void
 mepcop1_32_extract_sfmt_cpmovfrcsar0_C3 (mepcop1_32_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_32_insn_word base_insn, mepcop1_32_insn_word entire_insn){
     mepcop1_32_insn_word insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_cpfsftbi_C3.f
@@ -2641,6 +2694,56 @@ mepcop1_32_extract_sfmt_cpmovtocsar0_C3 (mepcop1_32_scache* abuf, mep_ext1_cpu*
 }
 
 void
+mepcop1_32_extract_sfmt_cpmovtocsar1_C3 (mepcop1_32_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_32_insn_word base_insn, mepcop1_32_insn_word entire_insn){
+    mepcop1_32_insn_word insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cpmoviu_h_C3.f
+    UINT f_ivc2_5u21;
+
+    f_ivc2_5u21 = EXTRACT_MSB0_UINT (insn, 32, 21, 5);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_ivc2_5u21) = f_ivc2_5u21;
+  if (UNLIKELY(current_cpu->trace_extract_p))
+    {
+      current_cpu->trace_stream 
+        << "0x" << hex << pc << dec << " (sfmt_cpmovtocsar1_C3)\t"
+        << " f_ivc2_5u21:0x" << hex << f_ivc2_5u21 << dec
+        << endl;
+    }
+
+  /* Record the fields for profiling.  */
+  if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
+    {
+    }
+#undef FLD
+}
+
+void
+mepcop1_32_extract_sfmt_cpmovtocc_C3 (mepcop1_32_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_32_insn_word base_insn, mepcop1_32_insn_word entire_insn){
+    mepcop1_32_insn_word insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cpmoviu_h_C3.f
+    UINT f_ivc2_5u21;
+
+    f_ivc2_5u21 = EXTRACT_MSB0_UINT (insn, 32, 21, 5);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_ivc2_5u21) = f_ivc2_5u21;
+  if (UNLIKELY(current_cpu->trace_extract_p))
+    {
+      current_cpu->trace_stream 
+        << "0x" << hex << pc << dec << " (sfmt_cpmovtocc_C3)\t"
+        << " f_ivc2_5u21:0x" << hex << f_ivc2_5u21 << dec
+        << endl;
+    }
+
+  /* Record the fields for profiling.  */
+  if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
+    {
+    }
+#undef FLD
+}
+
+void
 mepcop1_32_extract_sfmt_cpmov_C3 (mepcop1_32_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_32_insn_word base_insn, mepcop1_32_insn_word entire_insn){
     mepcop1_32_insn_word insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_cpfsftbi_C3.f
@@ -2862,7 +2965,7 @@ mepcop1_32_extract_sfmt_cpmovi_b_C3 (mepcop1_32_scache* abuf, mep_ext1_cpu* curr
     INT f_ivc2_8s4;
     UINT f_ivc2_5u21;
 
-    f_ivc2_8s4 = EXTRACT_MSB0_INT (insn, 32, 4, 8);
+    f_ivc2_8s4 = EXTRACT_MSB0_SINT (insn, 32, 4, 8);
     f_ivc2_5u21 = EXTRACT_MSB0_UINT (insn, 32, 21, 5);
 
   /* Record the fields for the semantic handler.  */
@@ -2914,6 +3017,205 @@ mepcop1_32_extract_sfmt_cpmoviu_h_C3 (mepcop1_32_scache* abuf, mep_ext1_cpu* cur
 }
 
 void
+mepcop1_32_extract_sfmt_cpadda1u_b_C3 (mepcop1_32_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_32_insn_word base_insn, mepcop1_32_insn_word entire_insn){
+    mepcop1_32_insn_word insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cdsrli3_C3.f
+    UINT f_ivc2_5u21;
+    UINT f_ivc2_5u26;
+
+    f_ivc2_5u21 = EXTRACT_MSB0_UINT (insn, 32, 21, 5);
+    f_ivc2_5u26 = EXTRACT_MSB0_UINT (insn, 32, 26, 5);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_ivc2_5u26) = f_ivc2_5u26;
+  FLD (f_ivc2_5u21) = f_ivc2_5u21;
+  if (UNLIKELY(current_cpu->trace_extract_p))
+    {
+      current_cpu->trace_stream 
+        << "0x" << hex << pc << dec << " (sfmt_cpadda1u_b_C3)\t"
+        << " f_ivc2_5u26:0x" << hex << f_ivc2_5u26 << dec
+        << " f_ivc2_5u21:0x" << hex << f_ivc2_5u21 << dec
+        << endl;
+    }
+
+  /* Record the fields for profiling.  */
+  if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
+    {
+    }
+#undef FLD
+}
+
+void
+mepcop1_32_extract_sfmt_cpaddua1_h_C3 (mepcop1_32_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_32_insn_word base_insn, mepcop1_32_insn_word entire_insn){
+    mepcop1_32_insn_word insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cdsrli3_C3.f
+    UINT f_ivc2_5u21;
+    UINT f_ivc2_5u26;
+
+    f_ivc2_5u21 = EXTRACT_MSB0_UINT (insn, 32, 21, 5);
+    f_ivc2_5u26 = EXTRACT_MSB0_UINT (insn, 32, 26, 5);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_ivc2_5u26) = f_ivc2_5u26;
+  FLD (f_ivc2_5u21) = f_ivc2_5u21;
+  if (UNLIKELY(current_cpu->trace_extract_p))
+    {
+      current_cpu->trace_stream 
+        << "0x" << hex << pc << dec << " (sfmt_cpaddua1_h_C3)\t"
+        << " f_ivc2_5u26:0x" << hex << f_ivc2_5u26 << dec
+        << " f_ivc2_5u21:0x" << hex << f_ivc2_5u21 << dec
+        << endl;
+    }
+
+  /* Record the fields for profiling.  */
+  if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
+    {
+    }
+#undef FLD
+}
+
+void
+mepcop1_32_extract_sfmt_cpaddla1_h_C3 (mepcop1_32_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_32_insn_word base_insn, mepcop1_32_insn_word entire_insn){
+    mepcop1_32_insn_word insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cdsrli3_C3.f
+    UINT f_ivc2_5u21;
+    UINT f_ivc2_5u26;
+
+    f_ivc2_5u21 = EXTRACT_MSB0_UINT (insn, 32, 21, 5);
+    f_ivc2_5u26 = EXTRACT_MSB0_UINT (insn, 32, 26, 5);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_ivc2_5u26) = f_ivc2_5u26;
+  FLD (f_ivc2_5u21) = f_ivc2_5u21;
+  if (UNLIKELY(current_cpu->trace_extract_p))
+    {
+      current_cpu->trace_stream 
+        << "0x" << hex << pc << dec << " (sfmt_cpaddla1_h_C3)\t"
+        << " f_ivc2_5u26:0x" << hex << f_ivc2_5u26 << dec
+        << " f_ivc2_5u21:0x" << hex << f_ivc2_5u21 << dec
+        << endl;
+    }
+
+  /* Record the fields for profiling.  */
+  if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
+    {
+    }
+#undef FLD
+}
+
+void
+mepcop1_32_extract_sfmt_cpaddaca1u_b_C3 (mepcop1_32_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_32_insn_word base_insn, mepcop1_32_insn_word entire_insn){
+    mepcop1_32_insn_word insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cdsrli3_C3.f
+    UINT f_ivc2_5u21;
+    UINT f_ivc2_5u26;
+
+    f_ivc2_5u21 = EXTRACT_MSB0_UINT (insn, 32, 21, 5);
+    f_ivc2_5u26 = EXTRACT_MSB0_UINT (insn, 32, 26, 5);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_ivc2_5u26) = f_ivc2_5u26;
+  FLD (f_ivc2_5u21) = f_ivc2_5u21;
+  if (UNLIKELY(current_cpu->trace_extract_p))
+    {
+      current_cpu->trace_stream 
+        << "0x" << hex << pc << dec << " (sfmt_cpaddaca1u_b_C3)\t"
+        << " f_ivc2_5u26:0x" << hex << f_ivc2_5u26 << dec
+        << " f_ivc2_5u21:0x" << hex << f_ivc2_5u21 << dec
+        << endl;
+    }
+
+  /* Record the fields for profiling.  */
+  if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
+    {
+    }
+#undef FLD
+}
+
+void
+mepcop1_32_extract_sfmt_cpaddacua1_h_C3 (mepcop1_32_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_32_insn_word base_insn, mepcop1_32_insn_word entire_insn){
+    mepcop1_32_insn_word insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cdsrli3_C3.f
+    UINT f_ivc2_5u21;
+    UINT f_ivc2_5u26;
+
+    f_ivc2_5u21 = EXTRACT_MSB0_UINT (insn, 32, 21, 5);
+    f_ivc2_5u26 = EXTRACT_MSB0_UINT (insn, 32, 26, 5);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_ivc2_5u26) = f_ivc2_5u26;
+  FLD (f_ivc2_5u21) = f_ivc2_5u21;
+  if (UNLIKELY(current_cpu->trace_extract_p))
+    {
+      current_cpu->trace_stream 
+        << "0x" << hex << pc << dec << " (sfmt_cpaddacua1_h_C3)\t"
+        << " f_ivc2_5u26:0x" << hex << f_ivc2_5u26 << dec
+        << " f_ivc2_5u21:0x" << hex << f_ivc2_5u21 << dec
+        << endl;
+    }
+
+  /* Record the fields for profiling.  */
+  if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
+    {
+    }
+#undef FLD
+}
+
+void
+mepcop1_32_extract_sfmt_cpaddacla1_h_C3 (mepcop1_32_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_32_insn_word base_insn, mepcop1_32_insn_word entire_insn){
+    mepcop1_32_insn_word insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cdsrli3_C3.f
+    UINT f_ivc2_5u21;
+    UINT f_ivc2_5u26;
+
+    f_ivc2_5u21 = EXTRACT_MSB0_UINT (insn, 32, 21, 5);
+    f_ivc2_5u26 = EXTRACT_MSB0_UINT (insn, 32, 26, 5);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_ivc2_5u26) = f_ivc2_5u26;
+  FLD (f_ivc2_5u21) = f_ivc2_5u21;
+  if (UNLIKELY(current_cpu->trace_extract_p))
+    {
+      current_cpu->trace_stream 
+        << "0x" << hex << pc << dec << " (sfmt_cpaddacla1_h_C3)\t"
+        << " f_ivc2_5u26:0x" << hex << f_ivc2_5u26 << dec
+        << " f_ivc2_5u21:0x" << hex << f_ivc2_5u21 << dec
+        << endl;
+    }
+
+  /* Record the fields for profiling.  */
+  if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
+    {
+    }
+#undef FLD
+}
+
+void
+mepcop1_32_extract_sfmt_cpsrla1_C3 (mepcop1_32_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_32_insn_word base_insn, mepcop1_32_insn_word entire_insn){
+    mepcop1_32_insn_word insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cpmoviu_h_C3.f
+    UINT f_ivc2_5u21;
+
+    f_ivc2_5u21 = EXTRACT_MSB0_UINT (insn, 32, 21, 5);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_ivc2_5u21) = f_ivc2_5u21;
+  if (UNLIKELY(current_cpu->trace_extract_p))
+    {
+      current_cpu->trace_stream 
+        << "0x" << hex << pc << dec << " (sfmt_cpsrla1_C3)\t"
+        << " f_ivc2_5u21:0x" << hex << f_ivc2_5u21 << dec
+        << endl;
+    }
+
+  /* Record the fields for profiling.  */
+  if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
+    {
+    }
+#undef FLD
+}
+
+void
 mepcop1_32_extract_sfmt_cpsrlia1_P1 (mepcop1_32_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_32_insn_word base_insn, mepcop1_32_insn_word entire_insn){
     mepcop1_32_insn_word insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_cpfsftbi_C3.f