* cgen-cpu.h: Update for new location of cgen/bitset.h.

[pf3gnuchains/pf3gnuchains4x.git] / sid / component / cgen-cpu / mep / mep-cop1-48-decode.cxx

diff --git a/sid/component/cgen-cpu/mep/mep-cop1-48-decode.cxx b/sid/component/cgen-cpu/mep/mep-cop1-48-decode.cxx
index efc3e32..9f65531 100644 (file)
--- a/sid/component/cgen-cpu/mep/mep-cop1-48-decode.cxx
+++ b/sid/component/cgen-cpu/mep/mep-cop1-48-decode.cxx
@@ -68,10 +68,10 @@ mepcop1_48_idesc mepcop1_48_idesc::idesc_table[MEPCOP1_48_INSN_CDMOVI_P0_P1 + 1]
   { mepcop1_48_sem_cpsub3_h_P0_P1, "CPSUB3_H_P0_P1", MEPCOP1_48_INSN_CPSUB3_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
   { mepcop1_48_sem_cpsub3_w_P0_P1, "CPSUB3_W_P0_P1", MEPCOP1_48_INSN_CPSUB3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
   { mepcop1_48_sem_cdsub3_P0_P1, "CDSUB3_P0_P1", MEPCOP1_48_INSN_CDSUB3_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
-  { mepcop1_48_sem_cpsadd3_h_P0_P1, "CPSADD3_H_P0_P1", MEPCOP1_48_INSN_CPSADD3_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
-  { mepcop1_48_sem_cpsadd3_w_P0_P1, "CPSADD3_W_P0_P1", MEPCOP1_48_INSN_CPSADD3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
-  { mepcop1_48_sem_cpssub3_h_P0_P1, "CPSSUB3_H_P0_P1", MEPCOP1_48_INSN_CPSSUB3_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
-  { mepcop1_48_sem_cpssub3_w_P0_P1, "CPSSUB3_W_P0_P1", MEPCOP1_48_INSN_CPSSUB3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+  { mepcop1_48_sem_cpsadd3_h_P0_P1, "CPSADD3_H_P0_P1", MEPCOP1_48_INSN_CPSADD3_H_P0_P1, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+  { mepcop1_48_sem_cpsadd3_w_P0_P1, "CPSADD3_W_P0_P1", MEPCOP1_48_INSN_CPSADD3_W_P0_P1, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+  { mepcop1_48_sem_cpssub3_h_P0_P1, "CPSSUB3_H_P0_P1", MEPCOP1_48_INSN_CPSSUB3_H_P0_P1, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+  { mepcop1_48_sem_cpssub3_w_P0_P1, "CPSSUB3_W_P0_P1", MEPCOP1_48_INSN_CPSSUB3_W_P0_P1, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
   { mepcop1_48_sem_cpextuaddu3_b_P0_P1, "CPEXTUADDU3_B_P0_P1", MEPCOP1_48_INSN_CPEXTUADDU3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
   { mepcop1_48_sem_cpextuadd3_b_P0_P1, "CPEXTUADD3_B_P0_P1", MEPCOP1_48_INSN_CPEXTUADD3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
   { mepcop1_48_sem_cpextladdu3_b_P0_P1, "CPEXTLADDU3_B_P0_P1", MEPCOP1_48_INSN_CPEXTLADDU3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
@@ -129,8 +129,8 @@ mepcop1_48_idesc mepcop1_48_idesc::idesc_table[MEPCOP1_48_INSN_CDMOVI_P0_P1 + 1]
   { mepcop1_48_sem_cpsll3_w_P0_P1, "CPSLL3_W_P0_P1", MEPCOP1_48_INSN_CPSLL3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
   { mepcop1_48_sem_cpssll3_w_P0_P1, "CPSSLL3_W_P0_P1", MEPCOP1_48_INSN_CPSSLL3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
   { mepcop1_48_sem_cdsll3_P0_P1, "CDSLL3_P0_P1", MEPCOP1_48_INSN_CDSLL3_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
-  { mepcop1_48_sem_cpsla3_h_P0_P1, "CPSLA3_H_P0_P1", MEPCOP1_48_INSN_CPSLA3_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
-  { mepcop1_48_sem_cpsla3_w_P0_P1, "CPSLA3_W_P0_P1", MEPCOP1_48_INSN_CPSLA3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+  { mepcop1_48_sem_cpsla3_h_P0_P1, "CPSLA3_H_P0_P1", MEPCOP1_48_INSN_CPSLA3_H_P0_P1, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+  { mepcop1_48_sem_cpsla3_w_P0_P1, "CPSLA3_W_P0_P1", MEPCOP1_48_INSN_CPSLA3_W_P0_P1, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
   { mepcop1_48_sem_cpsrli3_b_P0_P1, "CPSRLI3_B_P0_P1", MEPCOP1_48_INSN_CPSRLI3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
   { mepcop1_48_sem_cpsrli3_h_P0_P1, "CPSRLI3_H_P0_P1", MEPCOP1_48_INSN_CPSRLI3_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
   { mepcop1_48_sem_cpsrli3_w_P0_P1, "CPSRLI3_W_P0_P1", MEPCOP1_48_INSN_CPSRLI3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
@@ -143,8 +143,8 @@ mepcop1_48_idesc mepcop1_48_idesc::idesc_table[MEPCOP1_48_INSN_CDMOVI_P0_P1 + 1]
   { mepcop1_48_sem_cpslli3_h_P0_P1, "CPSLLI3_H_P0_P1", MEPCOP1_48_INSN_CPSLLI3_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
   { mepcop1_48_sem_cpslli3_w_P0_P1, "CPSLLI3_W_P0_P1", MEPCOP1_48_INSN_CPSLLI3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
   { mepcop1_48_sem_cdslli3_P0_P1, "CDSLLI3_P0_P1", MEPCOP1_48_INSN_CDSLLI3_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
-  { mepcop1_48_sem_cpslai3_h_P0_P1, "CPSLAI3_H_P0_P1", MEPCOP1_48_INSN_CPSLAI3_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
-  { mepcop1_48_sem_cpslai3_w_P0_P1, "CPSLAI3_W_P0_P1", MEPCOP1_48_INSN_CPSLAI3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+  { mepcop1_48_sem_cpslai3_h_P0_P1, "CPSLAI3_H_P0_P1", MEPCOP1_48_INSN_CPSLAI3_H_P0_P1, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+  { mepcop1_48_sem_cpslai3_w_P0_P1, "CPSLAI3_W_P0_P1", MEPCOP1_48_INSN_CPSLAI3_W_P0_P1, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
   { mepcop1_48_sem_cpclipiu3_w_P0_P1, "CPCLIPIU3_W_P0_P1", MEPCOP1_48_INSN_CPCLIPIU3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
   { mepcop1_48_sem_cpclipi3_w_P0_P1, "CPCLIPI3_W_P0_P1", MEPCOP1_48_INSN_CPCLIPI3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
   { mepcop1_48_sem_cdclipiu3_P0_P1, "CDCLIPIU3_P0_P1", MEPCOP1_48_INSN_CDCLIPIU3_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },