* cgen-engine.h (EXTRACT_MSB0_LGSINT, EXTRACT_MSB0_LGUINT): Define.

[pf3gnuchains/pf3gnuchains3x.git] / sim / m32r / decodex.c

diff --git a/sim/m32r/decodex.c b/sim/m32r/decodex.c
index f1644b9..1b58320 100644 (file)
--- a/sim/m32r/decodex.c
+++ b/sim/m32r/decodex.c
@@ -252,14 +252,14 @@ m32rxf_init_idesc_table (SIM_CPU *cpu)
 
 const IDESC *
 m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
-              CGEN_INSN_INT base_insn, CGEN_INSN_INT entire_insn,
+              CGEN_INSN_WORD base_insn, CGEN_INSN_WORD entire_insn,
               ARGBUF *abuf)
 {
   /* Result of decoder.  */
   M32RXF_INSN_TYPE itype;
 
   {
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 
     {
       unsigned int val = (((insn >> 8) & (15 << 4)) | ((insn >> 4) & (15 << 0)));
@@ -716,7 +716,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_add:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_add.f
     UINT f_r1;
     UINT f_r2;
@@ -747,7 +747,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_add3:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_add3.f
     UINT f_r1;
     UINT f_r2;
@@ -780,7 +780,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_and3:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_and3.f
     UINT f_r1;
     UINT f_r2;
@@ -813,7 +813,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_or3:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_and3.f
     UINT f_r1;
     UINT f_r2;
@@ -846,7 +846,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_addi:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_addi.f
     UINT f_r1;
     INT f_simm8;
@@ -875,7 +875,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_addv:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_add.f
     UINT f_r1;
     UINT f_r2;
@@ -906,7 +906,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_addv3:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_add3.f
     UINT f_r1;
     UINT f_r2;
@@ -939,7 +939,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_addx:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_add.f
     UINT f_r1;
     UINT f_r2;
@@ -970,7 +970,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_bc8:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_bl8.f
     SI f_disp8;
 
@@ -993,7 +993,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_bc24:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_bl24.f
     SI f_disp24;
 
@@ -1016,7 +1016,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_beq:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_beq.f
     UINT f_r1;
     UINT f_r2;
@@ -1049,7 +1049,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_beqz:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_beq.f
     UINT f_r2;
     SI f_disp16;
@@ -1077,7 +1077,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_bl8:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_bl8.f
     SI f_disp8;
 
@@ -1101,7 +1101,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_bl24:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_bl24.f
     SI f_disp24;
 
@@ -1125,7 +1125,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_bcl8:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_bl8.f
     SI f_disp8;
 
@@ -1149,7 +1149,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_bcl24:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_bl24.f
     SI f_disp24;
 
@@ -1173,7 +1173,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_bra8:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_bl8.f
     SI f_disp8;
 
@@ -1196,7 +1196,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_bra24:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_bl24.f
     SI f_disp24;
 
@@ -1219,7 +1219,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_cmp:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_st_plus.f
     UINT f_r1;
     UINT f_r2;
@@ -1249,7 +1249,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_cmpi:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_st_d.f
     UINT f_r2;
     INT f_simm16;
@@ -1277,7 +1277,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_cmpz:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_st_plus.f
     UINT f_r2;
 
@@ -1302,7 +1302,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_div:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_add.f
     UINT f_r1;
     UINT f_r2;
@@ -1333,7 +1333,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_jc:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_jl.f
     UINT f_r2;
 
@@ -1358,7 +1358,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_jl:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_jl.f
     UINT f_r2;
 
@@ -1384,7 +1384,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_jmp:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_jl.f
     UINT f_r2;
 
@@ -1409,7 +1409,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_ld:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_ld_plus.f
     UINT f_r1;
     UINT f_r2;
@@ -1439,7 +1439,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_ld_d:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_add3.f
     UINT f_r1;
     UINT f_r2;
@@ -1472,7 +1472,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_ldb:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_ld_plus.f
     UINT f_r1;
     UINT f_r2;
@@ -1502,7 +1502,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_ldb_d:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_add3.f
     UINT f_r1;
     UINT f_r2;
@@ -1535,7 +1535,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_ldh:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_ld_plus.f
     UINT f_r1;
     UINT f_r2;
@@ -1565,7 +1565,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_ldh_d:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_add3.f
     UINT f_r1;
     UINT f_r2;
@@ -1598,7 +1598,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_ld_plus:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_ld_plus.f
     UINT f_r1;
     UINT f_r2;
@@ -1629,7 +1629,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_ld24:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_ld24.f
     UINT f_r1;
     UINT f_uimm24;
@@ -1657,7 +1657,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_ldi8:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_addi.f
     UINT f_r1;
     INT f_simm8;
@@ -1685,7 +1685,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_ldi16:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_add3.f
     UINT f_r1;
     INT f_simm16;
@@ -1713,7 +1713,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_lock:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_ld_plus.f
     UINT f_r1;
     UINT f_r2;
@@ -1743,7 +1743,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_machi_a:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_machi_a.f
     UINT f_r1;
     UINT f_acc;
@@ -1776,7 +1776,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_mulhi_a:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_machi_a.f
     UINT f_r1;
     UINT f_acc;
@@ -1809,7 +1809,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_mv:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_ld_plus.f
     UINT f_r1;
     UINT f_r2;
@@ -1839,7 +1839,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_mvfachi_a:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_mvfachi_a.f
     UINT f_r1;
     UINT f_accs;
@@ -1867,7 +1867,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_mvfc:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_ld_plus.f
     UINT f_r1;
     UINT f_r2;
@@ -1895,7 +1895,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_mvtachi_a:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_mvtachi_a.f
     UINT f_r1;
     UINT f_accs;
@@ -1923,7 +1923,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_mvtc:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_ld_plus.f
     UINT f_r1;
     UINT f_r2;
@@ -1964,7 +1964,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_rac_dsi:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_rac_dsi.f
     UINT f_accd;
     UINT f_accs;
@@ -2006,7 +2006,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_seth:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_seth.f
     UINT f_r1;
     UINT f_hi16;
@@ -2034,7 +2034,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_sll3:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_add3.f
     UINT f_r1;
     UINT f_r2;
@@ -2067,7 +2067,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_slli:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_slli.f
     UINT f_r1;
     UINT f_uimm5;
@@ -2096,7 +2096,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_st:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_st_plus.f
     UINT f_r1;
     UINT f_r2;
@@ -2126,7 +2126,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_st_d:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_st_d.f
     UINT f_r1;
     UINT f_r2;
@@ -2159,7 +2159,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_stb:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_st_plus.f
     UINT f_r1;
     UINT f_r2;
@@ -2189,7 +2189,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_stb_d:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_st_d.f
     UINT f_r1;
     UINT f_r2;
@@ -2222,7 +2222,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_sth:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_st_plus.f
     UINT f_r1;
     UINT f_r2;
@@ -2252,7 +2252,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_sth_d:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_st_d.f
     UINT f_r1;
     UINT f_r2;
@@ -2285,7 +2285,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_st_plus:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_st_plus.f
     UINT f_r1;
     UINT f_r2;
@@ -2316,7 +2316,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_sth_plus:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_st_plus.f
     UINT f_r1;
     UINT f_r2;
@@ -2347,7 +2347,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_stb_plus:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_st_plus.f
     UINT f_r1;
     UINT f_r2;
@@ -2378,7 +2378,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_trap:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_trap.f
     UINT f_uimm4;
 
@@ -2401,7 +2401,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_unlock:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_st_plus.f
     UINT f_r1;
     UINT f_r2;
@@ -2431,7 +2431,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_satb:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_ld_plus.f
     UINT f_r1;
     UINT f_r2;
@@ -2461,7 +2461,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_sat:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_ld_plus.f
     UINT f_r1;
     UINT f_r2;
@@ -2504,7 +2504,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_macwu1:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_st_plus.f
     UINT f_r1;
     UINT f_r2;
@@ -2534,7 +2534,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_msblo:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_st_plus.f
     UINT f_r1;
     UINT f_r2;
@@ -2564,7 +2564,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_mulwu1:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_st_plus.f
     UINT f_r1;
     UINT f_r2;
@@ -2607,7 +2607,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_clrpsw:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_clrpsw.f
     UINT f_uimm8;
 
@@ -2624,7 +2624,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_setpsw:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_clrpsw.f
     UINT f_uimm8;
 
@@ -2641,7 +2641,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_bset:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_bset.f
     UINT f_uimm3;
     UINT f_r2;
@@ -2672,7 +2672,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_btst:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_bset.f
     UINT f_uimm3;
     UINT f_r2;