--- /dev/null
+//Original:/testcases/core/c_dsp32shiftim_lhalf_lp/c_dsp32shiftim_lhalf_lp.dsp
+// Spec Reference: dspshiftimm dreg_lo(hi) = lshift (dreg_lo(hi) by imm5)
+# mach: bfin
+
+.include "testutils.inc"
+ start
+
+
+
+// lshift : positive data, count (+)=left (half reg)
+// d_lo = lshift (d_lo BY imm5)
+// RLx by imm5
+imm32 r0, 0x00100a00;
+imm32 r1, 0x00100a01;
+imm32 r2, 0x00100a02;
+imm32 r3, 0x00100a03;
+imm32 r4, 0x00100a04;
+imm32 r5, 0x00100a05;
+imm32 r6, 0x00100a06;
+imm32 r7, 0x00100a07;
+R7.L = R0.L << 0;
+R0.L = R1.L << 1;
+R1.L = R2.L << 2;
+R2.L = R3.L << 3;
+R3.L = R4.L << 4;
+R4.L = R5.L << 5;
+R5.L = R6.L << 6;
+R6.L = R7.L << 7;
+CHECKREG r1, 0x00102808;
+CHECKREG r0, 0x00101402;
+CHECKREG r2, 0x00105018;
+CHECKREG r3, 0x0010A040;
+CHECKREG r4, 0x001040A0;
+CHECKREG r5, 0x00108180;
+CHECKREG r6, 0x00100000;
+CHECKREG r7, 0x00100A00;
+
+imm32 r0, 0x00200018;
+imm32 r1, 0x00200019;
+imm32 r2, 0x0020001a;
+imm32 r3, 0x0020001b;
+imm32 r4, 0x0020001c;
+imm32 r5, 0x0020001d;
+imm32 r6, 0x0020001e;
+imm32 r7, 0x0020001f;
+R2.L = R0.L << 8;
+R3.L = R1.L << 9;
+R4.L = R2.L << 10;
+R5.L = R3.L << 11;
+R6.L = R4.L << 12;
+R7.L = R5.L << 13;
+R0.L = R6.L << 14;
+R1.L = R7.L << 15;
+CHECKREG r0, 0x00200000;
+CHECKREG r1, 0x00200000;
+CHECKREG r2, 0x00201800;
+CHECKREG r3, 0x00203200;
+CHECKREG r4, 0x00200000;
+CHECKREG r5, 0x00200000;
+CHECKREG r6, 0x00200000;
+CHECKREG r7, 0x00200000;
+
+imm32 r0, 0x05002001;
+imm32 r1, 0x05002001;
+imm32 r2, 0x0500000f;
+imm32 r3, 0x05002003;
+imm32 r4, 0x05002004;
+imm32 r5, 0x05002005;
+imm32 r6, 0x05002006;
+imm32 r7, 0x05002007;
+R3.L = R0.L << 0;
+R4.L = R1.L << 1;
+R5.L = R2.L << 2;
+R6.L = R3.L << 3;
+R7.L = R4.L << 4;
+R0.L = R5.L << 5;
+R1.L = R6.L << 6;
+R2.L = R7.L << 7;
+CHECKREG r0, 0x05000780;
+CHECKREG r1, 0x05000200;
+CHECKREG r2, 0x05001000;
+CHECKREG r3, 0x05002001;
+CHECKREG r4, 0x05004002;
+CHECKREG r5, 0x0500003C;
+CHECKREG r6, 0x05000008;
+CHECKREG r7, 0x05000020;
+
+imm32 r0, 0x03000031;
+imm32 r1, 0x03000031;
+imm32 r2, 0x03000032;
+imm32 r3, 0x03000030;
+imm32 r4, 0x03000034;
+imm32 r5, 0x03000035;
+imm32 r6, 0x03000036;
+imm32 r7, 0x03000037;
+R4.L = R0.L << 8;
+R5.L = R1.L << 9;
+R6.L = R2.L << 10;
+R7.L = R3.L << 11;
+R0.L = R4.L << 12;
+R1.L = R5.L << 13;
+R2.L = R6.L << 14;
+R3.L = R7.L << 15;
+CHECKREG r0, 0x03000000;
+CHECKREG r1, 0x03000000;
+CHECKREG r2, 0x03000000;
+CHECKREG r3, 0x03000000;
+CHECKREG r4, 0x03003100;
+CHECKREG r5, 0x03006200;
+CHECKREG r6, 0x0300C800;
+CHECKREG r7, 0x03008000;
+// RHx by RLx
+imm32 r0, 0x03000000;
+imm32 r1, 0x03000000;
+imm32 r2, 0x03000000;
+imm32 r3, 0x03000000;
+imm32 r4, 0x03003100;
+imm32 r5, 0x03006200;
+imm32 r6, 0x0300C800;
+imm32 r7, 0x03008000;
+R5.L = R0.H << 0;
+R6.L = R1.H << 1;
+R7.L = R2.H << 2;
+R0.L = R3.H << 3;
+R1.L = R4.H << 4;
+R2.L = R5.H << 5;
+R3.L = R6.H << 6;
+R4.L = R7.H << 7;
+CHECKREG r0, 0x03001800;
+CHECKREG r1, 0x03003000;
+CHECKREG r2, 0x03006000;
+CHECKREG r3, 0x0300C000;
+CHECKREG r4, 0x03008000;
+CHECKREG r5, 0x03000300;
+CHECKREG r6, 0x03000600;
+CHECKREG r7, 0x03000C00;
+
+imm32 r0, 0x05018000;
+imm32 r1, 0x05018001;
+imm32 r2, 0x05028000;
+imm32 r3, 0x05038000;
+imm32 r4, 0x05048000;
+imm32 r5, 0x05058000;
+imm32 r6, 0x05068000;
+imm32 r7, 0x05078000;
+R6.L = R0.H << 8;
+R7.L = R1.H << 9;
+R0.L = R2.H << 10;
+R1.L = R3.H << 11;
+R2.L = R4.H << 12;
+R3.L = R5.H << 13;
+R4.L = R6.H << 14;
+R5.L = R7.H << 15;
+CHECKREG r0, 0x05010800;
+CHECKREG r1, 0x05011800;
+CHECKREG r2, 0x05024000;
+CHECKREG r3, 0x0503A000;
+CHECKREG r4, 0x05048000;
+CHECKREG r5, 0x05058000;
+CHECKREG r6, 0x05060100;
+CHECKREG r7, 0x05070200;
+
+
+imm32 r0, 0x60019000;
+imm32 r1, 0x60019000;
+imm32 r2, 0x6002900f;
+imm32 r3, 0x60039000;
+imm32 r4, 0x60049000;
+imm32 r5, 0x60059000;
+imm32 r6, 0x60069000;
+imm32 r7, 0x60079000;
+R7.L = R0.H << 0;
+R0.L = R1.H << 1;
+R1.L = R2.H << 2;
+R2.L = R3.H << 3;
+R3.L = R4.H << 4;
+R4.L = R5.H << 5;
+R5.L = R6.H << 6;
+R6.L = R7.H << 7;
+CHECKREG r0, 0x6001C002;
+CHECKREG r1, 0x60018008;
+CHECKREG r2, 0x60020018;
+CHECKREG r3, 0x60030040;
+CHECKREG r4, 0x600400A0;
+CHECKREG r5, 0x60050180;
+CHECKREG r6, 0x60060380;
+CHECKREG r7, 0x60076001;
+
+imm32 r0, 0x70010001;
+imm32 r1, 0x70010001;
+imm32 r2, 0x70020002;
+imm32 r3, 0x77030010;
+imm32 r4, 0x70040004;
+imm32 r5, 0x70050005;
+imm32 r6, 0x70060006;
+imm32 r7, 0x70070007;
+R0.L = R0.H << 8;
+R1.L = R1.H << 9;
+R2.L = R2.H << 10;
+R3.L = R3.H << 11;
+R4.L = R4.H << 12;
+R5.L = R5.H << 13;
+R6.L = R6.H << 14;
+R7.L = R7.H << 15;
+CHECKREG r0, 0x70010100;
+CHECKREG r1, 0x70010200;
+CHECKREG r2, 0x70020800;
+CHECKREG r3, 0x77031800;
+CHECKREG r4, 0x70044000;
+CHECKREG r5, 0x7005A000;
+CHECKREG r6, 0x70068000;
+CHECKREG r7, 0x70078000;
+
+// d_hi = lshft (d_lo BY d_lo)
+// RLx by RLx
+imm32 r0, 0xa8000000;
+imm32 r1, 0xa8000001;
+imm32 r2, 0xa8000002;
+imm32 r3, 0xa8000003;
+imm32 r4, 0xa8000004;
+imm32 r5, 0xa8000005;
+imm32 r6, 0xa8000006;
+imm32 r7, 0xa8000007;
+R0.H = R0.L << 0;
+R1.H = R1.L << 1;
+R2.H = R2.L << 2;
+R3.H = R3.L << 3;
+R4.H = R4.L << 4;
+R5.H = R5.L << 5;
+R6.H = R6.L << 6;
+R7.H = R7.L << 7;
+CHECKREG r0, 0x00000000;
+CHECKREG r1, 0x00020001;
+CHECKREG r2, 0x00080002;
+CHECKREG r3, 0x00180003;
+CHECKREG r4, 0x00400004;
+CHECKREG r5, 0x00A00005;
+CHECKREG r6, 0x01800006;
+CHECKREG r7, 0x03800007;
+
+imm32 r0, 0xf0090001;
+imm32 r1, 0xf0090001;
+imm32 r2, 0xf0090002;
+imm32 r3, 0xf0090003;
+imm32 r4, 0xf0090004;
+imm32 r5, 0xf0090005;
+imm32 r6, 0xf0000006;
+imm32 r7, 0xf0000007;
+R1.H = R0.L << 8;
+R2.H = R1.L << 9;
+R3.H = R2.L << 10;
+R4.H = R3.L << 11;
+R5.H = R4.L << 12;
+R6.H = R5.L << 13;
+R7.H = R6.L << 14;
+R0.H = R7.L << 15;
+CHECKREG r1, 0x01000001;
+CHECKREG r2, 0x02000002;
+CHECKREG r3, 0x08000003;
+CHECKREG r4, 0x18000004;
+CHECKREG r5, 0x40000005;
+CHECKREG r6, 0xA0000006;
+CHECKREG r7, 0x80000007;
+CHECKREG r0, 0x80000001;
+
+
+imm32 r0, 0x07000001;
+imm32 r1, 0x07000001;
+imm32 r2, 0x0700000f;
+imm32 r3, 0x07000003;
+imm32 r4, 0x07000004;
+imm32 r5, 0x07000005;
+imm32 r6, 0x07000006;
+imm32 r7, 0x07000007;
+R3.H = R0.L << 0;
+R4.H = R1.L << 1;
+R5.H = R2.L << 2;
+R6.H = R3.L << 3;
+R7.H = R4.L << 4;
+R0.H = R5.L << 5;
+R1.H = R6.L << 6;
+R2.H = R7.L << 7;
+CHECKREG r0, 0x00A00001;
+CHECKREG r1, 0x01800001;
+CHECKREG r2, 0x0380000F;
+CHECKREG r3, 0x00010003;
+CHECKREG r4, 0x00020004;
+CHECKREG r5, 0x003C0005;
+CHECKREG r6, 0x00180006;
+CHECKREG r7, 0x00400007;
+
+imm32 r0, 0x00000501;
+imm32 r1, 0x00000501;
+imm32 r2, 0x00000502;
+imm32 r3, 0x00000510;
+imm32 r4, 0x00000504;
+imm32 r5, 0x00000505;
+imm32 r6, 0x00000506;
+imm32 r7, 0x00000507;
+R4.H = R0.L << 8;
+R5.H = R1.L << 9;
+R6.H = R2.L << 10;
+R7.H = R3.L << 11;
+R0.H = R4.L << 12;
+R1.H = R5.L << 13;
+R2.H = R6.L << 14;
+R3.H = R7.L << 15;
+CHECKREG r0, 0x40000501;
+CHECKREG r1, 0xA0000501;
+CHECKREG r2, 0x80000502;
+CHECKREG r3, 0x80000510;
+CHECKREG r4, 0x01000504;
+CHECKREG r5, 0x02000505;
+CHECKREG r6, 0x08000506;
+CHECKREG r7, 0x80000507;
+
+imm32 r0, 0x00a00800;
+imm32 r1, 0x00a10800;
+imm32 r2, 0x00a20800;
+imm32 r3, 0x00a30800;
+imm32 r4, 0x00a40800;
+imm32 r5, 0x00a50800;
+imm32 r6, 0x00a60800;
+imm32 r7, 0x00a70800;
+R5.H = R0.H << 0;
+R6.H = R1.H << 1;
+R7.H = R2.H << 2;
+R0.H = R3.H << 3;
+R1.H = R4.H << 4;
+R2.H = R5.H << 5;
+R3.H = R6.H << 6;
+R4.H = R7.H << 7;
+CHECKREG r0, 0x05180800;
+CHECKREG r1, 0x0A400800;
+CHECKREG r2, 0x14000800;
+CHECKREG r3, 0x50800800;
+CHECKREG r4, 0x44000800;
+CHECKREG r5, 0x00A00800;
+CHECKREG r6, 0x01420800;
+CHECKREG r7, 0x02880800;
+
+imm32 r0, 0x0c010000;
+imm32 r1, 0x0c010001;
+imm32 r2, 0x0c020000;
+imm32 r3, 0x0c030000;
+imm32 r4, 0x0c040000;
+imm32 r5, 0x0c050000;
+imm32 r6, 0x0c060000;
+imm32 r7, 0x0c070000;
+R6.H = R0.H << 8;
+R7.H = R1.H << 9;
+R0.H = R2.H << 10;
+R1.H = R3.H << 11;
+R2.H = R4.H << 12;
+R3.H = R5.H << 13;
+R4.H = R6.H << 14;
+R5.H = R7.H << 15;
+CHECKREG r0, 0x08000000;
+CHECKREG r1, 0x18000001;
+CHECKREG r2, 0x40000000;
+CHECKREG r3, 0xA0000000;
+CHECKREG r4, 0x00000000;
+CHECKREG r5, 0x00000000;
+CHECKREG r6, 0x01000000;
+CHECKREG r7, 0x02000000;
+
+
+imm32 r0, 0x00b10000;
+imm32 r1, 0x00b10000;
+imm32 r2, 0x00b2000f;
+imm32 r3, 0x00b30000;
+imm32 r4, 0x00b40000;
+imm32 r5, 0x00b50000;
+imm32 r6, 0x00b60000;
+imm32 r7, 0x00b70000;
+R7.L = R0.H << 0;
+R0.L = R1.H << 1;
+R1.L = R2.H << 2;
+R2.L = R3.H << 3;
+R3.L = R4.H << 4;
+R4.L = R5.H << 5;
+R5.L = R6.H << 6;
+R6.L = R7.H << 7;
+CHECKREG r0, 0x00B10162;
+CHECKREG r1, 0x00B102C8;
+CHECKREG r2, 0x00B20598;
+CHECKREG r3, 0x00B30B40;
+CHECKREG r4, 0x00B416A0;
+CHECKREG r5, 0x00B52D80;
+CHECKREG r6, 0x00B65B80;
+CHECKREG r7, 0x00B700B1;
+
+imm32 r0, 0x0a010700;
+imm32 r1, 0x0a010700;
+imm32 r2, 0x0a020700;
+imm32 r3, 0x0a030710;
+imm32 r4, 0x0a040700;
+imm32 r5, 0x0a050700;
+imm32 r6, 0x0a060700;
+imm32 r7, 0x0a070700;
+R0.H = R0.H << 8;
+R1.H = R1.H << 9;
+R2.H = R2.H << 10;
+R3.H = R3.H << 11;
+R4.H = R4.H << 12;
+R5.H = R5.H << 13;
+R6.H = R6.H << 14;
+R7.H = R7.H << 15;
+CHECKREG r0, 0x01000700;
+CHECKREG r1, 0x02000700;
+CHECKREG r2, 0x08000700;
+CHECKREG r3, 0x18000710;
+CHECKREG r4, 0x40000700;
+CHECKREG r5, 0xA0000700;
+CHECKREG r6, 0x80000700;
+CHECKREG r7, 0x80000700;
+
+pass
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