ppu addr reset latch timing changed.

[motonesfpga/motonesfpga.git] / simulation / ppu / ppu.vhd

diff --git a/simulation/ppu/ppu.vhd b/simulation/ppu/ppu.vhd
index 8b41b3c..e33065c 100644 (file)
--- a/simulation/ppu/ppu.vhd
+++ b/simulation/ppu/ppu.vhd
@@ -161,6 +161,7 @@ signal ppu_addr_inc32   : std_logic_vector (13 downto 0);
 signal ppu_addr_in      : std_logic_vector (13 downto 0);
 signal ppu_addr_cnt     : std_logic_vector (0 downto 0);
 signal ppu_data         : std_logic_vector (dsize - 1 downto 0);
+signal ppu_data_in      : std_logic_vector (dsize - 1 downto 0);
 signal ppu_data_out     : std_logic_vector (dsize - 1 downto 0);
 signal read_data_n      : std_logic;
 signal ppu_latch_rst_n  : std_logic;
@@ -169,8 +170,9 @@ signal v_bus_busy_n     : std_logic;
 signal oam_bus_ce_n     : std_logic;
 signal plt_bus_ce_n     : std_logic;
 
-signal oam_plt_addr     : std_logic_vector (7 downto 0);
-signal oam_plt_data     : std_logic_vector (7 downto 0);
+signal oam_plt_addr     : std_logic_vector (dsize - 1 downto 0);
+signal oam_plt_data     : std_logic_vector (dsize - 1 downto 0);
+signal plt_data_out     : std_logic_vector (dsize - 1 downto 0);
 
 begin
 
@@ -227,17 +229,18 @@ begin
     ppu_data_inst : d_flip_flop generic map(dsize)
             port map (clk_n, rst_n, '1', ppu_data_we_n, cpu_d, ppu_data);
 
+    ppu_data_in_inst : d_flip_flop generic map(dsize)
+            port map (clk_n, rst_n, '1', ppu_data_we_n, vram_ad, ppu_data_in);
+
     ppu_data_out_inst : d_flip_flop generic map(dsize)
-            port map (clk_n, rst_n, '1', read_data_n, ppu_data, ppu_data_out);
+            port map (read_data_n, rst_n, '1', '0', ppu_data_in, ppu_data_out);
 
+    plt_data_out_inst : d_flip_flop generic map(dsize)
+            port map (clk_n, rst_n, '1', ppu_data_we_n, oam_plt_data, plt_data_out);
 
     reg_set_p : process (rst_n, ce_n, r_nw, cpu_addr, cpu_d, 
                         ppu_status(ST_VBL), ppu_ctrl(PPUNEN))
     begin
-        if (rst_n = '0') then
-            ppu_latch_rst_n <= '0';
-            vblank_n <= '1';
-        end if;
 
         if (ppu_status(ST_VBL)'event or ppu_ctrl(PPUNEN)'event) then
             if (ppu_status(ST_VBL) = '1' and ppu_ctrl(PPUNEN) = '1') then
@@ -249,7 +252,9 @@ begin
             end if;
         end if;
 
-        if (rst_n = '1' and ce_n = '0') then
+        if (rst_n = '0') then
+            vblank_n <= '1';
+        elsif (rst_n = '1' and ce_n = '0') then
 
             --register set.
             if(cpu_addr = PPUCTRL) then
@@ -265,12 +270,9 @@ begin
             end if;
 
             if(cpu_addr = PPUSTATUS and r_nw = '1') then
-                --reading status resets ppu_addr/scroll cnt.
-                ppu_latch_rst_n <= '0';
                 --notify reading status
                 read_status <= '1';
             else
-                ppu_latch_rst_n <= '1';
                 read_status <= '0';
             end if;
 
@@ -302,7 +304,6 @@ begin
             end if;
 
             if(cpu_addr = PPUADDR) then
-                ppu_addr_cnt_ce_n <= '0';
                 ppu_addr_we_n <= '0';
                 if (ppu_addr_cnt(0) = '0') then
                     ppu_addr_in <= cpu_d(5 downto 0) & ppu_addr(7 downto 0);
@@ -310,11 +311,10 @@ begin
                     ppu_addr_in <= ppu_addr(13 downto 8) & cpu_d;
                 end if;
             else
-                ppu_addr_cnt_ce_n <= '1';
                 ppu_addr_we_n <= '1';
             end if;
 
-            if (cpu_addr = PPUDATA and r_nw = '0') then
+            if (cpu_addr = PPUDATA and r_nw = '1') then
                 read_data_n <= '0';
             else
                 read_data_n <= '1';
@@ -328,7 +328,6 @@ begin
             ppu_scroll_y_we_n    <= '1';
             ppu_scroll_cnt_ce_n  <= '1';
             ppu_addr_we_n        <= '1';
-            ppu_addr_cnt_ce_n    <= '1';
             read_status <= '0';
             read_data_n <= '1';
         end if; --if (rst_n = '1' and ce_n = '0') 
@@ -339,7 +338,9 @@ begin
     clk_cnt_set_p : process (rst_n, ce_n, r_nw, cpu_addr, cpu_d, clk, 
                                 oam_plt_data, vram_ad, ppu_stat_out)
     begin
-        if (rst_n = '1' and ce_n = '0') then
+        if (rst_n = '0') then
+            ppu_latch_rst_n <= '0';
+        elsif (rst_n = '1' and ce_n = '0') then
             --set counter=0 on register write.   
             if (ce_n'event or r_nw'event or cpu_addr'event or (cpu_d'event and r_nw = '0')) then
                 ppu_clk_cnt_res_n <= '0';
@@ -353,6 +354,13 @@ begin
                 elsif (ppu_clk_cnt = "00") then
                     ppu_clk_cnt_res_n <= '1';
                 end if;
+
+                if (read_status = '1') then
+                    --reading status resets ppu_addr/scroll cnt.
+                    ppu_latch_rst_n <= '0';
+                else
+                    ppu_latch_rst_n <= '1';
+                end if;
                 --d_print("clk event");
             end if;
 
@@ -376,6 +384,7 @@ begin
 
             --vram address access.
             if (cpu_addr = PPUADDR and ppu_clk_cnt = "00") then
+                ppu_addr_cnt_ce_n <= '0';
                 if (ppu_addr_cnt(0) = '0') then
                     --load addr high
                     ale <= '0';
@@ -393,6 +402,7 @@ begin
                     end if;
                 end if;
             elsif (cpu_addr = PPUDATA and ppu_clk_cnt = "01") then
+                ppu_addr_cnt_ce_n <= '1';
                 --for burst write.
                 if (ppu_addr(13 downto 8) = "111111") then
                     oam_plt_addr <= ppu_addr(7 downto 0);
@@ -403,6 +413,7 @@ begin
                     ale <= '1';
                 end if;
             else
+                ppu_addr_cnt_ce_n <= '1';
                 ale <= '0';
             end if; --if (cpu_addr = PPUADDR and ppu_clk_cnt = "00") then
 
@@ -427,20 +438,23 @@ begin
                     if (r_nw = '0') then
                         vram_ad <= cpu_d;
                     else
-                        vram_ad <= (others => 'Z');
-                        cpu_d <= vram_ad;
+                        cpu_d <= ppu_data_out;
                     end if;
                 end if;
             else
                 plt_bus_ce_n <= '1';
                 ppu_data_we_n <= '1';
-                rd_n <= '1';
-                wr_n <= '1';
+                rd_n <= 'Z';
+                wr_n <= 'Z';
             end if; --if (cpu_addr = PPUDATA and ppu_clk_cnt = "00") then
 
             --sustain cpu output data when reading.
             if (cpu_addr = PPUDATA and r_nw = '1' and ppu_clk_cnt /= "00") then
-                cpu_d <= ppu_data;
+                if (ppu_addr(13 downto 8) = "111111") then
+                    cpu_d <= plt_data_out;
+                else
+                    cpu_d <= ppu_data_out;
+                end if;
             end if;
             if (cpu_addr = OAMDATA and r_nw = '1' and ppu_clk_cnt /= "00") then
                 cpu_d <= oam_data;
@@ -456,6 +470,8 @@ begin
             ppu_clk_cnt_res_n <= '0';
             oam_bus_ce_n     <= '1';
             oam_addr_ce_n <= '1';
+            ppu_addr_cnt_ce_n    <= '1';
+            ppu_latch_rst_n <= '1';
 
             rd_n <= 'Z';
             wr_n <= 'Z';
@@ -464,7 +480,7 @@ begin
             vram_ad <= (others => 'Z');
             vram_a <= (others => 'Z');
             cpu_d <= (others => 'Z');
-        end if; --if (rst_n = '1' and ce_n = '0') then
+        end if; --if (rst_n = '0') then
     end process;
 
 end rtl;