[VM] Add vm_template.h . This class, VM_TEMPLATE:: must be mother of VM:: .See fm7...

[csp-qt/common_source_project-fm7.git] / source / src / vm / fm7 / fm7_mainio.cpp

diff --git a/source/src/vm/fm7/fm7_mainio.cpp b/source/src/vm/fm7/fm7_mainio.cpp
index 56f7ea3..63c71fd 100644 (file)
--- a/source/src/vm/fm7/fm7_mainio.cpp
+++ b/source/src/vm/fm7/fm7_mainio.cpp
@@ -32,11 +32,9 @@
 #endif
 #include "../../statesub.h"
 
-FM7_MAINIO::FM7_MAINIO(VM* parent_vm, EMU* parent_emu) : DEVICE(parent_vm, parent_emu)
+FM7_MAINIO::FM7_MAINIO(VM_TEMPLATE* parent_vm, EMU* parent_emu) : DEVICE(parent_vm, parent_emu)
 {
        int i;
-       p_vm = parent_vm;
-       p_emu = parent_emu;
        for(i = 0; i < 3; i++) {
                opn[i] = NULL;
        }
@@ -129,6 +127,7 @@ FM7_MAINIO::FM7_MAINIO(VM* parent_vm, EMU* parent_emu) : DEVICE(parent_vm, paren
                opn_address[i] = 0x00;
                opn_data[i] = 0x00;
                opn_cmdreg[i] = 0;
+               opn_prescaler_type[i] = 1;
        }
        intstat_whg = false;
        intstat_thg = false;
@@ -192,7 +191,6 @@ FM7_MAINIO::FM7_MAINIO(VM* parent_vm, EMU* parent_emu) : DEVICE(parent_vm, paren
        initialize_output_signals(&nmi_bus);
        
        set_device_name(_T("MAIN I/O"));
-       decl_state();
 }
 
 FM7_MAINIO::~FM7_MAINIO()
@@ -230,7 +228,7 @@ void FM7_MAINIO::initialize()
        event_2hd_nmi = -1;
        nmi_delay = 300;
 #endif
-       reset_printer();
+       //reset_printer();
 }
 
 void FM7_MAINIO::reset()
@@ -1963,11 +1961,13 @@ void FM7_MAINIO::event_vline(int v, int clock)
 {
 }
 
-//#define STATE_VERSION 13
-#define STATE_VERSION 14
+
+#define STATE_VERSION 16
+#include "../../statesub.h"
+
 void FM7_MAINIO::decl_state(void)
 {
-       state_entry = new csp_state_utils(STATE_VERSION, this_device_id, _T("FM7_MAINIO"));
+       enter_decl_state(STATE_VERSION);
 
        DECL_STATE_ENTRY_MULTI(void, io_w_latch, sizeof(io_w_latch));
        
@@ -2110,7 +2110,7 @@ void FM7_MAINIO::decl_state(void)
        DECL_STATE_ENTRY_UINT8(fdc_2HD_datareg);
        DECL_STATE_ENTRY_UINT8(fdc_2HD_headreg);
        DECL_STATE_ENTRY_UINT8(fdc_2HD_drvsel);
-       DECL_STATE_ENTRY_BOOL(irqreg_fdc_2HD);
+       DECL_STATE_ENTRY_UINT8(irqreg_fdc_2HD);
        DECL_STATE_ENTRY_BOOL(fdc_2HD_motor);
        //state_fio->FputBool(irqstat_fdc);
        DECL_STATE_ENTRY_INT(event_2hd_nmi);
@@ -2118,27 +2118,31 @@ void FM7_MAINIO::decl_state(void)
        DECL_STATE_ENTRY_BOOL(irqstat_fdc_2hd);
        DECL_STATE_ENTRY_BOOL(drqstat_fdc_2hd);
 #endif
-       DECL_STATE_ENTRY_BOOL(connect_opn);
-       DECL_STATE_ENTRY_BOOL(connect_whg);
-       DECL_STATE_ENTRY_BOOL(connect_thg);
        
-       DECL_STATE_ENTRY_BOOL(opn_psg_77av);
-       DECL_STATE_ENTRY_UINT32_ARRAY(opn_address, 4);
-       DECL_STATE_ENTRY_UINT32_ARRAY(opn_data, 4);
-       DECL_STATE_ENTRY_UINT32_ARRAY(opn_stat, 4);
-       DECL_STATE_ENTRY_UINT8_ARRAY(opn_cmdreg, 4);
-       DECL_STATE_ENTRY_UINT8_ARRAY(opn_ch3mode, 4);
-       for(int ch = 0; ch < 4; ch++) {
-               DECL_STATE_ENTRY_MULTI(void, opn_regs[ch], 0x100 * sizeof(uint8_t));
-       }
-    
+       decl_state_opn();
+       
+       leave_decl_state();
 }
 void FM7_MAINIO::save_state(FILEIO *state_fio)
 {
        if(state_entry != NULL) state_entry->save_state(state_fio);
+#if 0
+       // Debug
+       for(int i = 0; i < 3; i++) {
+               out_debug_log("OPN#%d registers (to Save)", i);
+               out_debug_log("ADDR: +0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +a +b +c +d +e +f");
+               for(int ladr = 0; ladr < 0x100; ladr += 0x10) {
+                       out_debug_log("+%02x: %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
+                                                 ladr,
+                                                 opn_regs[i][ladr + 0],  opn_regs[i][ladr + 1],  opn_regs[i][ladr + 2],  opn_regs[i][ladr + 3],
+                                                 opn_regs[i][ladr + 4],  opn_regs[i][ladr + 5],  opn_regs[i][ladr + 6],  opn_regs[i][ladr + 7],
+                                                 opn_regs[i][ladr + 8],  opn_regs[i][ladr + 9],  opn_regs[i][ladr + 10], opn_regs[i][ladr + 11],
+                                                 opn_regs[i][ladr + 12], opn_regs[i][ladr + 13], opn_regs[i][ladr + 14], opn_regs[i][ladr + 15]);
+               }
+       }
+#endif 
 }
 
-
 bool FM7_MAINIO::load_state(FILEIO *state_fio)
 {
        int ch;
@@ -2148,10 +2152,26 @@ bool FM7_MAINIO::load_state(FILEIO *state_fio)
        bool mb = false;
        if(state_entry != NULL) {
                mb = state_entry->load_state(state_fio);
+               if(mb) {
 #if defined(HAS_DMA)
-               dma_addr = dma_addr & 0x1f;
+                       dma_addr = dma_addr & 0x1f;
 #endif
+               }
        }
+#if 0
+       for(int i = 0; i < 3; i++) {
+               out_debug_log("OPN#%d registers (Loaded)", i);
+               out_debug_log("ADDR: +0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +a +b +c +d +e +f");
+               for(int ladr = 0; ladr < 0x100; ladr += 0x10) {
+                       out_debug_log("+%02x: %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
+                                                 ladr,
+                                                 opn_regs[i][ladr + 0],  opn_regs[i][ladr + 1],  opn_regs[i][ladr + 2],  opn_regs[i][ladr + 3],
+                                                 opn_regs[i][ladr + 4],  opn_regs[i][ladr + 5],  opn_regs[i][ladr + 6],  opn_regs[i][ladr + 7],
+                                                 opn_regs[i][ladr + 8],  opn_regs[i][ladr + 9],  opn_regs[i][ladr + 10], opn_regs[i][ladr + 11],
+                                                 opn_regs[i][ladr + 12], opn_regs[i][ladr + 13], opn_regs[i][ladr + 14], opn_regs[i][ladr + 15]);
+               }
+       }
+#endif
        this->out_debug_log(_T("Load State: MAINIO: id=%d stat=%s\n"), this_device_id, (mb) ? _T("OK") : _T("NG"));
        return mb;
 }