#ifdef WITH_Z80
z80 = NULL;
#endif
+#if defined(CAPABLE_JCOMMCARD)
+ jcommcard = NULL;
+#endif
#if defined(_FM8)
bubble_casette[0] = NULL;
bubble_casette[1] = NULL;
initialize_output_signals(&printer_reset_bus);
initialize_output_signals(&printer_strobe_bus);
initialize_output_signals(&printer_select_bus);
+ initialize_output_signals(&irq_bus);
+ initialize_output_signals(&firq_bus);
+ initialize_output_signals(&nmi_bus);
set_device_name(_T("MAIN I/O"));
}
stat_fdmode_2hd = false; // R/W : bit6, '0' = 2HD, '1' = 2DD. FM-77 Only.
stat_kanjirom = true; // R/W : bit5, '0' = sub, '1' = main. FM-77 Only.
#endif
- maincpu->write_signal(SIG_CPU_FIRQ, 0, 1);
+ write_signals(&firq_bus, 0);
+
#if defined(HAS_DMA)
intstat_dma = false;
dma_addr = 0;
reg_fd12 = 0xbc; // 0b10111100
#endif
#if defined(WITH_Z80)
- z80->write_signal(SIG_CPU_BUSREQ, 0xffffffff, 0xffffffff);
+ if(z80 != NULL) z80->write_signal(SIG_CPU_BUSREQ, 0xffffffff, 0xffffffff);
#endif
maincpu->write_signal(SIG_CPU_BUSREQ, 0, 0xffffffff);
maincpu->write_signal(SIG_CPU_HALTREQ, 0, 0xffffffff);
-//#if defined(_FM8)
-// bubble_casette[0]->reset();
-// bubble_casette[1]->reset();
-//#endif
#if !defined(_FM8)
void FM7_MAINIO::do_irq(void)
{
bool intstat;
+ uint32_t nval;
#if defined(_FM8)
intstat = intstat_txrdy | intstat_rxrdy | intstat_syndet;
#else
# if defined(HAS_DMA)
intstat = intstat | intstat_dma;
# endif
-#endif
- //printf("%08d : IRQ: REG0=%02x FDC=%02x, stat=%d\n", SDL_GetTicks(), irqstat_reg0, irqstat_fdc, intstat);
- if(intstat) {
- maincpu->write_signal(SIG_CPU_IRQ, 1, 1);
- } else {
- maincpu->write_signal(SIG_CPU_IRQ, 0, 1);
- }
+#endif
+ nval = (intstat) ? 0xffffffff : 0;
+ write_signals(&irq_bus, nval);
}
void FM7_MAINIO::do_firq(void)
{
bool firq_stat;
+ uint32_t nval;
firq_stat = firq_break_key | firq_sub_attention;
- if(firq_stat) {
- maincpu->write_signal(SIG_CPU_FIRQ, 1, 1);
- } else {
- maincpu->write_signal(SIG_CPU_FIRQ, 0, 1);
- }
- //this->out_debug_log(_T("IO: do_firq(). BREAK=%d ATTN=%d"), firq_break_key ? 1 : 0, firq_sub_attention ? 1 : 0);
+ nval = (firq_stat) ? 0xffffffff : 0;
+ write_signals(&firq_bus, nval);
}
void FM7_MAINIO::do_nmi(bool flag)
{
- maincpu->write_signal(SIG_CPU_NMI, flag ? 1 : 0, 1);
+ write_signals(&nmi_bus, (flag) ? 0xffffffff : 0);
}
req_z80run = true;
} else {
req_z80run = false;
- z80->write_signal(SIG_CPU_BUSREQ, 1, 1);
+ if(z80 != NULL) z80->write_signal(SIG_CPU_BUSREQ, 1, 1);
}
#endif
}
#if defined(WITH_Z80)
case FM7_MAINIO_RUN_Z80:
if((req_z80run)/* && (val_b) */) {
- z80->write_signal(SIG_CPU_BUSREQ, 0, 1);
+ if(z80 != NULL) z80->write_signal(SIG_CPU_BUSREQ, 0, 1);
z80_run = true;
//z80->reset(); // OK?
}
case 0x23: // Kanji ROM
retval = (uint32_t) read_kanjidata_right();
break;
+#if defined(CAPABLE_JCOMMCARD)
+ case 0x28:
+ case 0x29:
+ case 0x2a:
+ case 0x2b:
+ if(jcommcard != NULL) {
+ retval = (uint32_t)(jcommcard->read_io8(addr));
+ } else {
+ retval = 0xff;
+ }
+ break;
+#endif
#if defined(CAPABLE_KANJI_CLASS2)
case 0x2e: // Kanji ROM Level2
retval = (uint32_t) read_kanjidata_left_l2();
//write_kanjiaddr_lo((uint8_t)data);
#endif
break;
+#if defined(CAPABLE_JCOMMCARD)
+ case 0x28:
+ case 0x29:
+ case 0x2a:
+ case 0x2b:
+ if(jcommcard != NULL) jcommcard->write_io8(addr, data);
+ break;
+#endif
#if defined(CAPABLE_DICTROM)
case 0x2e: //
mainmem->write_signal(FM7_MAINIO_EXTBANK, data, 0xff);
}
mainmem->write_signal(FM7_MAINIO_PUSH_FD0F, (config.boot_mode == 0) ? 1 : 0, 0x01);
mainmem->write_signal(FM7_MAINIO_BOOTMODE, bootmode, 0xffffffff);
-#endif
+#endif
}
void FM7_MAINIO::event_vline(int v, int clock)