#define SIG_MEMORY_SEL 0
+namespace SC3000 {
+
class MEMORY : public DEVICE
{
private:
void update_bank();
public:
- MEMORY(VM* parent_vm, EMU* parent_emu) : DEVICE(parent_vm, parent_emu)
+ MEMORY(VM_TEMPLATE* parent_vm, EMU* parent_emu) : DEVICE(parent_vm, parent_emu)
{
set_device_name(_T("Memory Bus"));
}
// common functions
void initialize();
- void write_data8(uint32_t addr, uint32_t data);
- uint32_t read_data8(uint32_t addr);
- void write_signal(int id, uint32_t data, uint32_t mask);
- void decl_state();
- void save_state(FILEIO* state_fio);
- bool load_state(FILEIO* state_fio);
+ void __FASTCALL write_data8(uint32_t addr, uint32_t data);
+ uint32_t __FASTCALL read_data8(uint32_t addr);
+ void __FASTCALL write_signal(int id, uint32_t data, uint32_t mask);
+ bool process_state(FILEIO* state_fio, bool loading);
// unique functions
void open_cart(const _TCHAR* file_path);
}
};
+}
#endif